1 //===-- SIOptimizeExecMaskingPreRA.cpp ------------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// This pass removes redundant S_OR_B64 instructions enabling lanes in 12 /// the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any 13 /// vector instructions between them we can only keep outer SI_END_CF, given 14 /// that CFG is structured and exec bits of the outer end statement are always 15 /// not less than exec bit of the inner one. 16 /// 17 /// This needs to be done before the RA to eliminate saved exec bits registers 18 /// but after register coalescer to have no vector registers copies in between 19 /// of different end cf statements. 20 /// 21 //===----------------------------------------------------------------------===// 22 23 #include "AMDGPU.h" 24 #include "AMDGPUSubtarget.h" 25 #include "SIInstrInfo.h" 26 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 27 #include "llvm/CodeGen/LiveIntervals.h" 28 #include "llvm/CodeGen/MachineFunctionPass.h" 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "si-optimize-exec-masking-pre-ra" 33 34 namespace { 35 36 class SIOptimizeExecMaskingPreRA : public MachineFunctionPass { 37 public: 38 static char ID; 39 40 public: 41 SIOptimizeExecMaskingPreRA() : MachineFunctionPass(ID) { 42 initializeSIOptimizeExecMaskingPreRAPass(*PassRegistry::getPassRegistry()); 43 } 44 45 bool runOnMachineFunction(MachineFunction &MF) override; 46 47 StringRef getPassName() const override { 48 return "SI optimize exec mask operations pre-RA"; 49 } 50 51 void getAnalysisUsage(AnalysisUsage &AU) const override { 52 AU.addRequired<LiveIntervals>(); 53 AU.setPreservesAll(); 54 MachineFunctionPass::getAnalysisUsage(AU); 55 } 56 }; 57 58 } // End anonymous namespace. 59 60 INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRA, DEBUG_TYPE, 61 "SI optimize exec mask operations pre-RA", false, false) 62 INITIALIZE_PASS_DEPENDENCY(LiveIntervals) 63 INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA, DEBUG_TYPE, 64 "SI optimize exec mask operations pre-RA", false, false) 65 66 char SIOptimizeExecMaskingPreRA::ID = 0; 67 68 char &llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID; 69 70 FunctionPass *llvm::createSIOptimizeExecMaskingPreRAPass() { 71 return new SIOptimizeExecMaskingPreRA(); 72 } 73 74 static bool isEndCF(const MachineInstr& MI, const SIRegisterInfo* TRI) { 75 return MI.getOpcode() == AMDGPU::S_OR_B64 && 76 MI.modifiesRegister(AMDGPU::EXEC, TRI); 77 } 78 79 static bool isFullExecCopy(const MachineInstr& MI) { 80 return MI.isFullCopy() && MI.getOperand(1).getReg() == AMDGPU::EXEC; 81 } 82 83 static unsigned getOrNonExecReg(const MachineInstr &MI, 84 const SIInstrInfo &TII) { 85 auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1); 86 if (Op->isReg() && Op->getReg() != AMDGPU::EXEC) 87 return Op->getReg(); 88 Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0); 89 if (Op->isReg() && Op->getReg() != AMDGPU::EXEC) 90 return Op->getReg(); 91 return AMDGPU::NoRegister; 92 } 93 94 static MachineInstr* getOrExecSource(const MachineInstr &MI, 95 const SIInstrInfo &TII, 96 const MachineRegisterInfo &MRI) { 97 auto SavedExec = getOrNonExecReg(MI, TII); 98 if (SavedExec == AMDGPU::NoRegister) 99 return nullptr; 100 auto SaveExecInst = MRI.getUniqueVRegDef(SavedExec); 101 if (!SaveExecInst || !isFullExecCopy(*SaveExecInst)) 102 return nullptr; 103 return SaveExecInst; 104 } 105 106 bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) { 107 if (skipFunction(MF.getFunction())) 108 return false; 109 110 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); 111 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 112 const SIInstrInfo *TII = ST.getInstrInfo(); 113 MachineRegisterInfo &MRI = MF.getRegInfo(); 114 LiveIntervals *LIS = &getAnalysis<LiveIntervals>(); 115 DenseSet<unsigned> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI}); 116 bool Changed = false; 117 118 for (MachineBasicBlock &MBB : MF) { 119 120 // Try to remove unneeded instructions before s_endpgm. 121 if (MBB.succ_empty()) { 122 if (MBB.empty() || MBB.back().getOpcode() != AMDGPU::S_ENDPGM) 123 continue; 124 125 SmallVector<MachineBasicBlock*, 4> Blocks({&MBB}); 126 127 while (!Blocks.empty()) { 128 auto CurBB = Blocks.pop_back_val(); 129 auto I = CurBB->rbegin(), E = CurBB->rend(); 130 if (I != E) { 131 if (I->isUnconditionalBranch() || I->getOpcode() == AMDGPU::S_ENDPGM) 132 ++I; 133 else if (I->isBranch()) 134 continue; 135 } 136 137 while (I != E) { 138 if (I->isDebugInstr()) { 139 I = std::next(I); 140 continue; 141 } 142 143 if (I->mayStore() || I->isBarrier() || I->isCall() || 144 I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef()) 145 break; 146 147 LLVM_DEBUG(dbgs() 148 << "Removing no effect instruction: " << *I << '\n'); 149 150 for (auto &Op : I->operands()) { 151 if (Op.isReg()) 152 RecalcRegs.insert(Op.getReg()); 153 } 154 155 auto Next = std::next(I); 156 LIS->RemoveMachineInstrFromMaps(*I); 157 I->eraseFromParent(); 158 I = Next; 159 160 Changed = true; 161 } 162 163 if (I != E) 164 continue; 165 166 // Try to ascend predecessors. 167 for (auto *Pred : CurBB->predecessors()) { 168 if (Pred->succ_size() == 1) 169 Blocks.push_back(Pred); 170 } 171 } 172 continue; 173 } 174 175 // Try to collapse adjacent endifs. 176 auto Lead = MBB.begin(), E = MBB.end(); 177 if (MBB.succ_size() != 1 || Lead == E || !isEndCF(*Lead, TRI)) 178 continue; 179 180 const MachineBasicBlock* Succ = *MBB.succ_begin(); 181 if (!MBB.isLayoutSuccessor(Succ)) 182 continue; 183 184 auto I = std::next(Lead); 185 186 for ( ; I != E; ++I) 187 if (!TII->isSALU(*I) || I->readsRegister(AMDGPU::EXEC, TRI)) 188 break; 189 190 if (I != E) 191 continue; 192 193 const auto NextLead = Succ->begin(); 194 if (NextLead == Succ->end() || !isEndCF(*NextLead, TRI) || 195 !getOrExecSource(*NextLead, *TII, MRI)) 196 continue; 197 198 LLVM_DEBUG(dbgs() << "Redundant EXEC = S_OR_B64 found: " << *Lead << '\n'); 199 200 auto SaveExec = getOrExecSource(*Lead, *TII, MRI); 201 unsigned SaveExecReg = getOrNonExecReg(*Lead, *TII); 202 for (auto &Op : Lead->operands()) { 203 if (Op.isReg()) 204 RecalcRegs.insert(Op.getReg()); 205 } 206 207 LIS->RemoveMachineInstrFromMaps(*Lead); 208 Lead->eraseFromParent(); 209 if (SaveExecReg) { 210 LIS->removeInterval(SaveExecReg); 211 LIS->createAndComputeVirtRegInterval(SaveExecReg); 212 } 213 214 Changed = true; 215 216 // If the only use of saved exec in the removed instruction is S_AND_B64 217 // fold the copy now. 218 if (!SaveExec || !SaveExec->isFullCopy()) 219 continue; 220 221 unsigned SavedExec = SaveExec->getOperand(0).getReg(); 222 bool SafeToReplace = true; 223 for (auto& U : MRI.use_nodbg_instructions(SavedExec)) { 224 if (U.getParent() != SaveExec->getParent()) { 225 SafeToReplace = false; 226 break; 227 } 228 229 LLVM_DEBUG(dbgs() << "Redundant EXEC COPY: " << *SaveExec << '\n'); 230 } 231 232 if (SafeToReplace) { 233 LIS->RemoveMachineInstrFromMaps(*SaveExec); 234 SaveExec->eraseFromParent(); 235 MRI.replaceRegWith(SavedExec, AMDGPU::EXEC); 236 LIS->removeInterval(SavedExec); 237 } 238 } 239 240 if (Changed) { 241 for (auto Reg : RecalcRegs) { 242 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 243 LIS->removeInterval(Reg); 244 if (!MRI.reg_empty(Reg)) 245 LIS->createAndComputeVirtRegInterval(Reg); 246 } else { 247 for (MCRegUnitIterator U(Reg, TRI); U.isValid(); ++U) 248 LIS->removeRegUnit(*U); 249 } 250 } 251 } 252 253 return Changed; 254 } 255