1 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "SystemZMCTargetDesc.h" 11 #include "InstPrinter/SystemZInstPrinter.h" 12 #include "SystemZMCAsmInfo.h" 13 #include "llvm/MC/MCInstrInfo.h" 14 #include "llvm/MC/MCRegisterInfo.h" 15 #include "llvm/MC/MCStreamer.h" 16 #include "llvm/MC/MCSubtargetInfo.h" 17 #include "llvm/Support/TargetRegistry.h" 18 19 using namespace llvm; 20 21 #define GET_INSTRINFO_MC_DESC 22 #include "SystemZGenInstrInfo.inc" 23 24 #define GET_SUBTARGETINFO_MC_DESC 25 #include "SystemZGenSubtargetInfo.inc" 26 27 #define GET_REGINFO_MC_DESC 28 #include "SystemZGenRegisterInfo.inc" 29 30 const unsigned SystemZMC::GR32Regs[16] = { 31 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, 32 SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, 33 SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, 34 SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L 35 }; 36 37 const unsigned SystemZMC::GRH32Regs[16] = { 38 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, 39 SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, 40 SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, 41 SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H 42 }; 43 44 const unsigned SystemZMC::GR64Regs[16] = { 45 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 46 SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, 47 SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, 48 SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D 49 }; 50 51 const unsigned SystemZMC::GR128Regs[16] = { 52 SystemZ::R0Q, 0, SystemZ::R2Q, 0, 53 SystemZ::R4Q, 0, SystemZ::R6Q, 0, 54 SystemZ::R8Q, 0, SystemZ::R10Q, 0, 55 SystemZ::R12Q, 0, SystemZ::R14Q, 0 56 }; 57 58 const unsigned SystemZMC::FP32Regs[16] = { 59 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, 60 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, 61 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, 62 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S 63 }; 64 65 const unsigned SystemZMC::FP64Regs[16] = { 66 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, 67 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, 68 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, 69 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D 70 }; 71 72 const unsigned SystemZMC::FP128Regs[16] = { 73 SystemZ::F0Q, SystemZ::F1Q, 0, 0, 74 SystemZ::F4Q, SystemZ::F5Q, 0, 0, 75 SystemZ::F8Q, SystemZ::F9Q, 0, 0, 76 SystemZ::F12Q, SystemZ::F13Q, 0, 0 77 }; 78 79 const unsigned SystemZMC::VR32Regs[32] = { 80 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, 81 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, 82 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, 83 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, 84 SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, 85 SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, 86 SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, 87 SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S 88 }; 89 90 const unsigned SystemZMC::VR64Regs[32] = { 91 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, 92 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, 93 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, 94 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 95 SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, 96 SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, 97 SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, 98 SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D 99 }; 100 101 const unsigned SystemZMC::VR128Regs[32] = { 102 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, 103 SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, 104 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, 105 SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 106 SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, 107 SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, 108 SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, 109 SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31 110 }; 111 112 const unsigned SystemZMC::AR32Regs[16] = { 113 SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3, 114 SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7, 115 SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11, 116 SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15 117 }; 118 119 const unsigned SystemZMC::CR64Regs[16] = { 120 SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3, 121 SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7, 122 SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11, 123 SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15 124 }; 125 126 unsigned SystemZMC::getFirstReg(unsigned Reg) { 127 static unsigned Map[SystemZ::NUM_TARGET_REGS]; 128 static bool Initialized = false; 129 if (!Initialized) { 130 for (unsigned I = 0; I < 16; ++I) { 131 Map[GR32Regs[I]] = I; 132 Map[GRH32Regs[I]] = I; 133 Map[GR64Regs[I]] = I; 134 Map[GR128Regs[I]] = I; 135 Map[FP128Regs[I]] = I; 136 Map[AR32Regs[I]] = I; 137 } 138 for (unsigned I = 0; I < 32; ++I) { 139 Map[VR32Regs[I]] = I; 140 Map[VR64Regs[I]] = I; 141 Map[VR128Regs[I]] = I; 142 } 143 } 144 assert(Reg < SystemZ::NUM_TARGET_REGS); 145 return Map[Reg]; 146 } 147 148 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, 149 const Triple &TT) { 150 MCAsmInfo *MAI = new SystemZMCAsmInfo(TT); 151 MCCFIInstruction Inst = 152 MCCFIInstruction::createDefCfa(nullptr, 153 MRI.getDwarfRegNum(SystemZ::R15D, true), 154 SystemZMC::CFAOffsetFromInitialSP); 155 MAI->addInitialFrameState(Inst); 156 return MAI; 157 } 158 159 static MCInstrInfo *createSystemZMCInstrInfo() { 160 MCInstrInfo *X = new MCInstrInfo(); 161 InitSystemZMCInstrInfo(X); 162 return X; 163 } 164 165 static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) { 166 MCRegisterInfo *X = new MCRegisterInfo(); 167 InitSystemZMCRegisterInfo(X, SystemZ::R14D); 168 return X; 169 } 170 171 static MCSubtargetInfo * 172 createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { 173 return createSystemZMCSubtargetInfoImpl(TT, CPU, FS); 174 } 175 176 static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T, 177 unsigned SyntaxVariant, 178 const MCAsmInfo &MAI, 179 const MCInstrInfo &MII, 180 const MCRegisterInfo &MRI) { 181 return new SystemZInstPrinter(MAI, MII, MRI); 182 } 183 184 extern "C" void LLVMInitializeSystemZTargetMC() { 185 // Register the MCAsmInfo. 186 TargetRegistry::RegisterMCAsmInfo(getTheSystemZTarget(), 187 createSystemZMCAsmInfo); 188 189 // Register the MCCodeEmitter. 190 TargetRegistry::RegisterMCCodeEmitter(getTheSystemZTarget(), 191 createSystemZMCCodeEmitter); 192 193 // Register the MCInstrInfo. 194 TargetRegistry::RegisterMCInstrInfo(getTheSystemZTarget(), 195 createSystemZMCInstrInfo); 196 197 // Register the MCRegisterInfo. 198 TargetRegistry::RegisterMCRegInfo(getTheSystemZTarget(), 199 createSystemZMCRegisterInfo); 200 201 // Register the MCSubtargetInfo. 202 TargetRegistry::RegisterMCSubtargetInfo(getTheSystemZTarget(), 203 createSystemZMCSubtargetInfo); 204 205 // Register the MCAsmBackend. 206 TargetRegistry::RegisterMCAsmBackend(getTheSystemZTarget(), 207 createSystemZMCAsmBackend); 208 209 // Register the MCInstPrinter. 210 TargetRegistry::RegisterMCInstPrinter(getTheSystemZTarget(), 211 createSystemZMCInstPrinter); 212 } 213
