1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2010 4 * Vipin Kumar, ST Micoelectronics, vipin.kumar (at) st.com. 5 */ 6 7 /* 8 * Designware ethernet IP driver for U-Boot 9 */ 10 11 #include <common.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <miiphy.h> 16 #include <malloc.h> 17 #include <pci.h> 18 #include <linux/compiler.h> 19 #include <linux/err.h> 20 #include <linux/kernel.h> 21 #include <asm/io.h> 22 #include <power/regulator.h> 23 #include "designware.h" 24 25 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 26 { 27 #ifdef CONFIG_DM_ETH 28 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 29 struct eth_mac_regs *mac_p = priv->mac_regs_p; 30 #else 31 struct eth_mac_regs *mac_p = bus->priv; 32 #endif 33 ulong start; 34 u16 miiaddr; 35 int timeout = CONFIG_MDIO_TIMEOUT; 36 37 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 38 ((reg << MIIREGSHIFT) & MII_REGMSK); 39 40 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 41 42 start = get_timer(0); 43 while (get_timer(start) < timeout) { 44 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) 45 return readl(&mac_p->miidata); 46 udelay(10); 47 }; 48 49 return -ETIMEDOUT; 50 } 51 52 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 53 u16 val) 54 { 55 #ifdef CONFIG_DM_ETH 56 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 57 struct eth_mac_regs *mac_p = priv->mac_regs_p; 58 #else 59 struct eth_mac_regs *mac_p = bus->priv; 60 #endif 61 ulong start; 62 u16 miiaddr; 63 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; 64 65 writel(val, &mac_p->miidata); 66 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 67 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 68 69 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 70 71 start = get_timer(0); 72 while (get_timer(start) < timeout) { 73 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 74 ret = 0; 75 break; 76 } 77 udelay(10); 78 }; 79 80 return ret; 81 } 82 83 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) 84 static int dw_mdio_reset(struct mii_dev *bus) 85 { 86 struct udevice *dev = bus->priv; 87 struct dw_eth_dev *priv = dev_get_priv(dev); 88 struct dw_eth_pdata *pdata = dev_get_platdata(dev); 89 int ret; 90 91 if (!dm_gpio_is_valid(&priv->reset_gpio)) 92 return 0; 93 94 /* reset the phy */ 95 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 96 if (ret) 97 return ret; 98 99 udelay(pdata->reset_delays[0]); 100 101 ret = dm_gpio_set_value(&priv->reset_gpio, 1); 102 if (ret) 103 return ret; 104 105 udelay(pdata->reset_delays[1]); 106 107 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 108 if (ret) 109 return ret; 110 111 udelay(pdata->reset_delays[2]); 112 113 return 0; 114 } 115 #endif 116 117 static int dw_mdio_init(const char *name, void *priv) 118 { 119 struct mii_dev *bus = mdio_alloc(); 120 121 if (!bus) { 122 printf("Failed to allocate MDIO bus\n"); 123 return -ENOMEM; 124 } 125 126 bus->read = dw_mdio_read; 127 bus->write = dw_mdio_write; 128 snprintf(bus->name, sizeof(bus->name), "%s", name); 129 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) 130 bus->reset = dw_mdio_reset; 131 #endif 132 133 bus->priv = priv; 134 135 return mdio_register(bus); 136 } 137 138 static void tx_descs_init(struct dw_eth_dev *priv) 139 { 140 struct eth_dma_regs *dma_p = priv->dma_regs_p; 141 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 142 char *txbuffs = &priv->txbuffs[0]; 143 struct dmamacdescr *desc_p; 144 u32 idx; 145 146 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 147 desc_p = &desc_table_p[idx]; 148 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE]; 149 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; 150 151 #if defined(CONFIG_DW_ALTDESCRIPTOR) 152 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 153 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | 154 DESC_TXSTS_TXCHECKINSCTRL | 155 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 156 157 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 158 desc_p->dmamac_cntl = 0; 159 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 160 #else 161 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 162 desc_p->txrx_status = 0; 163 #endif 164 } 165 166 /* Correcting the last pointer of the chain */ 167 desc_p->dmamac_next = (ulong)&desc_table_p[0]; 168 169 /* Flush all Tx buffer descriptors at once */ 170 flush_dcache_range((ulong)priv->tx_mac_descrtable, 171 (ulong)priv->tx_mac_descrtable + 172 sizeof(priv->tx_mac_descrtable)); 173 174 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 175 priv->tx_currdescnum = 0; 176 } 177 178 static void rx_descs_init(struct dw_eth_dev *priv) 179 { 180 struct eth_dma_regs *dma_p = priv->dma_regs_p; 181 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 182 char *rxbuffs = &priv->rxbuffs[0]; 183 struct dmamacdescr *desc_p; 184 u32 idx; 185 186 /* Before passing buffers to GMAC we need to make sure zeros 187 * written there right after "priv" structure allocation were 188 * flushed into RAM. 189 * Otherwise there's a chance to get some of them flushed in RAM when 190 * GMAC is already pushing data to RAM via DMA. This way incoming from 191 * GMAC data will be corrupted. */ 192 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); 193 194 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 195 desc_p = &desc_table_p[idx]; 196 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 197 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; 198 199 desc_p->dmamac_cntl = 200 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | 201 DESC_RXCTRL_RXCHAIN; 202 203 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 204 } 205 206 /* Correcting the last pointer of the chain */ 207 desc_p->dmamac_next = (ulong)&desc_table_p[0]; 208 209 /* Flush all Rx buffer descriptors at once */ 210 flush_dcache_range((ulong)priv->rx_mac_descrtable, 211 (ulong)priv->rx_mac_descrtable + 212 sizeof(priv->rx_mac_descrtable)); 213 214 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 215 priv->rx_currdescnum = 0; 216 } 217 218 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) 219 { 220 struct eth_mac_regs *mac_p = priv->mac_regs_p; 221 u32 macid_lo, macid_hi; 222 223 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + 224 (mac_id[3] << 24); 225 macid_hi = mac_id[4] + (mac_id[5] << 8); 226 227 writel(macid_hi, &mac_p->macaddr0hi); 228 writel(macid_lo, &mac_p->macaddr0lo); 229 230 return 0; 231 } 232 233 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, 234 struct phy_device *phydev) 235 { 236 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; 237 238 if (!phydev->link) { 239 printf("%s: No link.\n", phydev->dev->name); 240 return 0; 241 } 242 243 if (phydev->speed != 1000) 244 conf |= MII_PORTSELECT; 245 else 246 conf &= ~MII_PORTSELECT; 247 248 if (phydev->speed == 100) 249 conf |= FES_100; 250 251 if (phydev->duplex) 252 conf |= FULLDPLXMODE; 253 254 writel(conf, &mac_p->conf); 255 256 printf("Speed: %d, %s duplex%s\n", phydev->speed, 257 (phydev->duplex) ? "full" : "half", 258 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 259 260 return 0; 261 } 262 263 static void _dw_eth_halt(struct dw_eth_dev *priv) 264 { 265 struct eth_mac_regs *mac_p = priv->mac_regs_p; 266 struct eth_dma_regs *dma_p = priv->dma_regs_p; 267 268 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); 269 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); 270 271 phy_shutdown(priv->phydev); 272 } 273 274 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) 275 { 276 struct eth_mac_regs *mac_p = priv->mac_regs_p; 277 struct eth_dma_regs *dma_p = priv->dma_regs_p; 278 unsigned int start; 279 int ret; 280 281 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); 282 283 /* 284 * When a MII PHY is used, we must set the PS bit for the DMA 285 * reset to succeed. 286 */ 287 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII) 288 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf); 289 else 290 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf); 291 292 start = get_timer(0); 293 while (readl(&dma_p->busmode) & DMAMAC_SRST) { 294 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { 295 printf("DMA reset timeout\n"); 296 return -ETIMEDOUT; 297 } 298 299 mdelay(100); 300 }; 301 302 /* 303 * Soft reset above clears HW address registers. 304 * So we have to set it here once again. 305 */ 306 _dw_write_hwaddr(priv, enetaddr); 307 308 rx_descs_init(priv); 309 tx_descs_init(priv); 310 311 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); 312 313 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE 314 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, 315 &dma_p->opmode); 316 #else 317 writel(readl(&dma_p->opmode) | FLUSHTXFIFO, 318 &dma_p->opmode); 319 #endif 320 321 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); 322 323 #ifdef CONFIG_DW_AXI_BURST_LEN 324 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); 325 #endif 326 327 /* Start up the PHY */ 328 ret = phy_startup(priv->phydev); 329 if (ret) { 330 printf("Could not initialize PHY %s\n", 331 priv->phydev->dev->name); 332 return ret; 333 } 334 335 ret = dw_adjust_link(priv, mac_p, priv->phydev); 336 if (ret) 337 return ret; 338 339 return 0; 340 } 341 342 int designware_eth_enable(struct dw_eth_dev *priv) 343 { 344 struct eth_mac_regs *mac_p = priv->mac_regs_p; 345 346 if (!priv->phydev->link) 347 return -EIO; 348 349 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 350 351 return 0; 352 } 353 354 #define ETH_ZLEN 60 355 356 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) 357 { 358 struct eth_dma_regs *dma_p = priv->dma_regs_p; 359 u32 desc_num = priv->tx_currdescnum; 360 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 361 ulong desc_start = (ulong)desc_p; 362 ulong desc_end = desc_start + 363 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 364 ulong data_start = desc_p->dmamac_addr; 365 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 366 /* 367 * Strictly we only need to invalidate the "txrx_status" field 368 * for the following check, but on some platforms we cannot 369 * invalidate only 4 bytes, so we flush the entire descriptor, 370 * which is 16 bytes in total. This is safe because the 371 * individual descriptors in the array are each aligned to 372 * ARCH_DMA_MINALIGN and padded appropriately. 373 */ 374 invalidate_dcache_range(desc_start, desc_end); 375 376 /* Check if the descriptor is owned by CPU */ 377 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 378 printf("CPU not owner of tx frame\n"); 379 return -EPERM; 380 } 381 382 length = max(length, ETH_ZLEN); 383 384 memcpy((void *)data_start, packet, length); 385 386 /* Flush data to be sent */ 387 flush_dcache_range(data_start, data_end); 388 389 #if defined(CONFIG_DW_ALTDESCRIPTOR) 390 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 391 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & 392 DESC_TXCTRL_SIZE1MASK; 393 394 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 395 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 396 #else 397 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & 398 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | 399 DESC_TXCTRL_TXFIRST; 400 401 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 402 #endif 403 404 /* Flush modified buffer descriptor */ 405 flush_dcache_range(desc_start, desc_end); 406 407 /* Test the wrap-around condition. */ 408 if (++desc_num >= CONFIG_TX_DESCR_NUM) 409 desc_num = 0; 410 411 priv->tx_currdescnum = desc_num; 412 413 /* Start the transmission */ 414 writel(POLL_DATA, &dma_p->txpolldemand); 415 416 return 0; 417 } 418 419 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) 420 { 421 u32 status, desc_num = priv->rx_currdescnum; 422 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 423 int length = -EAGAIN; 424 ulong desc_start = (ulong)desc_p; 425 ulong desc_end = desc_start + 426 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 427 ulong data_start = desc_p->dmamac_addr; 428 ulong data_end; 429 430 /* Invalidate entire buffer descriptor */ 431 invalidate_dcache_range(desc_start, desc_end); 432 433 status = desc_p->txrx_status; 434 435 /* Check if the owner is the CPU */ 436 if (!(status & DESC_RXSTS_OWNBYDMA)) { 437 438 length = (status & DESC_RXSTS_FRMLENMSK) >> 439 DESC_RXSTS_FRMLENSHFT; 440 441 /* Invalidate received data */ 442 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 443 invalidate_dcache_range(data_start, data_end); 444 *packetp = (uchar *)(ulong)desc_p->dmamac_addr; 445 } 446 447 return length; 448 } 449 450 static int _dw_free_pkt(struct dw_eth_dev *priv) 451 { 452 u32 desc_num = priv->rx_currdescnum; 453 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 454 ulong desc_start = (ulong)desc_p; 455 ulong desc_end = desc_start + 456 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 457 458 /* 459 * Make the current descriptor valid again and go to 460 * the next one 461 */ 462 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 463 464 /* Flush only status field - others weren't changed */ 465 flush_dcache_range(desc_start, desc_end); 466 467 /* Test the wrap-around condition. */ 468 if (++desc_num >= CONFIG_RX_DESCR_NUM) 469 desc_num = 0; 470 priv->rx_currdescnum = desc_num; 471 472 return 0; 473 } 474 475 static int dw_phy_init(struct dw_eth_dev *priv, void *dev) 476 { 477 struct phy_device *phydev; 478 int mask = 0xffffffff, ret; 479 480 #ifdef CONFIG_PHY_ADDR 481 mask = 1 << CONFIG_PHY_ADDR; 482 #endif 483 484 phydev = phy_find_by_mask(priv->bus, mask, priv->interface); 485 if (!phydev) 486 return -ENODEV; 487 488 phy_connect_dev(phydev, dev); 489 490 phydev->supported &= PHY_GBIT_FEATURES; 491 if (priv->max_speed) { 492 ret = phy_set_supported(phydev, priv->max_speed); 493 if (ret) 494 return ret; 495 } 496 phydev->advertising = phydev->supported; 497 498 priv->phydev = phydev; 499 phy_config(phydev); 500 501 return 0; 502 } 503 504 #ifndef CONFIG_DM_ETH 505 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 506 { 507 int ret; 508 509 ret = designware_eth_init(dev->priv, dev->enetaddr); 510 if (!ret) 511 ret = designware_eth_enable(dev->priv); 512 513 return ret; 514 } 515 516 static int dw_eth_send(struct eth_device *dev, void *packet, int length) 517 { 518 return _dw_eth_send(dev->priv, packet, length); 519 } 520 521 static int dw_eth_recv(struct eth_device *dev) 522 { 523 uchar *packet; 524 int length; 525 526 length = _dw_eth_recv(dev->priv, &packet); 527 if (length == -EAGAIN) 528 return 0; 529 net_process_received_packet(packet, length); 530 531 _dw_free_pkt(dev->priv); 532 533 return 0; 534 } 535 536 static void dw_eth_halt(struct eth_device *dev) 537 { 538 return _dw_eth_halt(dev->priv); 539 } 540 541 static int dw_write_hwaddr(struct eth_device *dev) 542 { 543 return _dw_write_hwaddr(dev->priv, dev->enetaddr); 544 } 545 546 int designware_initialize(ulong base_addr, u32 interface) 547 { 548 struct eth_device *dev; 549 struct dw_eth_dev *priv; 550 551 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 552 if (!dev) 553 return -ENOMEM; 554 555 /* 556 * Since the priv structure contains the descriptors which need a strict 557 * buswidth alignment, memalign is used to allocate memory 558 */ 559 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, 560 sizeof(struct dw_eth_dev)); 561 if (!priv) { 562 free(dev); 563 return -ENOMEM; 564 } 565 566 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { 567 printf("designware: buffers are outside DMA memory\n"); 568 return -EINVAL; 569 } 570 571 memset(dev, 0, sizeof(struct eth_device)); 572 memset(priv, 0, sizeof(struct dw_eth_dev)); 573 574 sprintf(dev->name, "dwmac.%lx", base_addr); 575 dev->iobase = (int)base_addr; 576 dev->priv = priv; 577 578 priv->dev = dev; 579 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 580 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 581 DW_DMA_BASE_OFFSET); 582 583 dev->init = dw_eth_init; 584 dev->send = dw_eth_send; 585 dev->recv = dw_eth_recv; 586 dev->halt = dw_eth_halt; 587 dev->write_hwaddr = dw_write_hwaddr; 588 589 eth_register(dev); 590 591 priv->interface = interface; 592 593 dw_mdio_init(dev->name, priv->mac_regs_p); 594 priv->bus = miiphy_get_dev_by_name(dev->name); 595 596 return dw_phy_init(priv, dev); 597 } 598 #endif 599 600 #ifdef CONFIG_DM_ETH 601 static int designware_eth_start(struct udevice *dev) 602 { 603 struct eth_pdata *pdata = dev_get_platdata(dev); 604 struct dw_eth_dev *priv = dev_get_priv(dev); 605 int ret; 606 607 ret = designware_eth_init(priv, pdata->enetaddr); 608 if (ret) 609 return ret; 610 ret = designware_eth_enable(priv); 611 if (ret) 612 return ret; 613 614 return 0; 615 } 616 617 int designware_eth_send(struct udevice *dev, void *packet, int length) 618 { 619 struct dw_eth_dev *priv = dev_get_priv(dev); 620 621 return _dw_eth_send(priv, packet, length); 622 } 623 624 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) 625 { 626 struct dw_eth_dev *priv = dev_get_priv(dev); 627 628 return _dw_eth_recv(priv, packetp); 629 } 630 631 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length) 632 { 633 struct dw_eth_dev *priv = dev_get_priv(dev); 634 635 return _dw_free_pkt(priv); 636 } 637 638 void designware_eth_stop(struct udevice *dev) 639 { 640 struct dw_eth_dev *priv = dev_get_priv(dev); 641 642 return _dw_eth_halt(priv); 643 } 644 645 int designware_eth_write_hwaddr(struct udevice *dev) 646 { 647 struct eth_pdata *pdata = dev_get_platdata(dev); 648 struct dw_eth_dev *priv = dev_get_priv(dev); 649 650 return _dw_write_hwaddr(priv, pdata->enetaddr); 651 } 652 653 static int designware_eth_bind(struct udevice *dev) 654 { 655 #ifdef CONFIG_DM_PCI 656 static int num_cards; 657 char name[20]; 658 659 /* Create a unique device name for PCI type devices */ 660 if (device_is_on_pci_bus(dev)) { 661 sprintf(name, "eth_designware#%u", num_cards++); 662 device_set_name(dev, name); 663 } 664 #endif 665 666 return 0; 667 } 668 669 int designware_eth_probe(struct udevice *dev) 670 { 671 struct eth_pdata *pdata = dev_get_platdata(dev); 672 struct dw_eth_dev *priv = dev_get_priv(dev); 673 u32 iobase = pdata->iobase; 674 ulong ioaddr; 675 int ret; 676 #ifdef CONFIG_CLK 677 int i, err, clock_nb; 678 679 priv->clock_count = 0; 680 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); 681 if (clock_nb > 0) { 682 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), 683 GFP_KERNEL); 684 if (!priv->clocks) 685 return -ENOMEM; 686 687 for (i = 0; i < clock_nb; i++) { 688 err = clk_get_by_index(dev, i, &priv->clocks[i]); 689 if (err < 0) 690 break; 691 692 err = clk_enable(&priv->clocks[i]); 693 if (err && err != -ENOSYS && err != -ENOTSUPP) { 694 pr_err("failed to enable clock %d\n", i); 695 clk_free(&priv->clocks[i]); 696 goto clk_err; 697 } 698 priv->clock_count++; 699 } 700 } else if (clock_nb != -ENOENT) { 701 pr_err("failed to get clock phandle(%d)\n", clock_nb); 702 return clock_nb; 703 } 704 #endif 705 706 #if defined(CONFIG_DM_REGULATOR) 707 struct udevice *phy_supply; 708 709 ret = device_get_supply_regulator(dev, "phy-supply", 710 &phy_supply); 711 if (ret) { 712 debug("%s: No phy supply\n", dev->name); 713 } else { 714 ret = regulator_set_enable(phy_supply, true); 715 if (ret) { 716 puts("Error enabling phy supply\n"); 717 return ret; 718 } 719 } 720 #endif 721 722 #ifdef CONFIG_DM_PCI 723 /* 724 * If we are on PCI bus, either directly attached to a PCI root port, 725 * or via a PCI bridge, fill in platdata before we probe the hardware. 726 */ 727 if (device_is_on_pci_bus(dev)) { 728 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); 729 iobase &= PCI_BASE_ADDRESS_MEM_MASK; 730 iobase = dm_pci_mem_to_phys(dev, iobase); 731 732 pdata->iobase = iobase; 733 pdata->phy_interface = PHY_INTERFACE_MODE_RMII; 734 } 735 #endif 736 737 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); 738 ioaddr = iobase; 739 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; 740 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); 741 priv->interface = pdata->phy_interface; 742 priv->max_speed = pdata->max_speed; 743 744 dw_mdio_init(dev->name, dev); 745 priv->bus = miiphy_get_dev_by_name(dev->name); 746 747 ret = dw_phy_init(priv, dev); 748 debug("%s, ret=%d\n", __func__, ret); 749 750 return ret; 751 752 #ifdef CONFIG_CLK 753 clk_err: 754 ret = clk_release_all(priv->clocks, priv->clock_count); 755 if (ret) 756 pr_err("failed to disable all clocks\n"); 757 758 return err; 759 #endif 760 } 761 762 static int designware_eth_remove(struct udevice *dev) 763 { 764 struct dw_eth_dev *priv = dev_get_priv(dev); 765 766 free(priv->phydev); 767 mdio_unregister(priv->bus); 768 mdio_free(priv->bus); 769 770 #ifdef CONFIG_CLK 771 return clk_release_all(priv->clocks, priv->clock_count); 772 #else 773 return 0; 774 #endif 775 } 776 777 const struct eth_ops designware_eth_ops = { 778 .start = designware_eth_start, 779 .send = designware_eth_send, 780 .recv = designware_eth_recv, 781 .free_pkt = designware_eth_free_pkt, 782 .stop = designware_eth_stop, 783 .write_hwaddr = designware_eth_write_hwaddr, 784 }; 785 786 int designware_eth_ofdata_to_platdata(struct udevice *dev) 787 { 788 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); 789 #ifdef CONFIG_DM_GPIO 790 struct dw_eth_dev *priv = dev_get_priv(dev); 791 #endif 792 struct eth_pdata *pdata = &dw_pdata->eth_pdata; 793 const char *phy_mode; 794 #ifdef CONFIG_DM_GPIO 795 int reset_flags = GPIOD_IS_OUT; 796 #endif 797 int ret = 0; 798 799 pdata->iobase = dev_read_addr(dev); 800 pdata->phy_interface = -1; 801 phy_mode = dev_read_string(dev, "phy-mode"); 802 if (phy_mode) 803 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 804 if (pdata->phy_interface == -1) { 805 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 806 return -EINVAL; 807 } 808 809 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); 810 811 #ifdef CONFIG_DM_GPIO 812 if (dev_read_bool(dev, "snps,reset-active-low")) 813 reset_flags |= GPIOD_ACTIVE_LOW; 814 815 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, 816 &priv->reset_gpio, reset_flags); 817 if (ret == 0) { 818 ret = dev_read_u32_array(dev, "snps,reset-delays-us", 819 dw_pdata->reset_delays, 3); 820 } else if (ret == -ENOENT) { 821 ret = 0; 822 } 823 #endif 824 825 return ret; 826 } 827 828 static const struct udevice_id designware_eth_ids[] = { 829 { .compatible = "allwinner,sun7i-a20-gmac" }, 830 { .compatible = "altr,socfpga-stmmac" }, 831 { .compatible = "amlogic,meson6-dwmac" }, 832 { .compatible = "amlogic,meson-gx-dwmac" }, 833 { .compatible = "st,stm32-dwmac" }, 834 { } 835 }; 836 837 U_BOOT_DRIVER(eth_designware) = { 838 .name = "eth_designware", 839 .id = UCLASS_ETH, 840 .of_match = designware_eth_ids, 841 .ofdata_to_platdata = designware_eth_ofdata_to_platdata, 842 .bind = designware_eth_bind, 843 .probe = designware_eth_probe, 844 .remove = designware_eth_remove, 845 .ops = &designware_eth_ops, 846 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 847 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata), 848 .flags = DM_FLAG_ALLOC_PRIV_DMA, 849 }; 850 851 static struct pci_device_id supported[] = { 852 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, 853 { } 854 }; 855 856 U_BOOT_PCI_DEVICE(eth_designware, supported); 857 #endif 858
