1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * 5 * FSL DCU Framebuffer driver 6 */ 7 8 #include <asm/io.h> 9 #include <common.h> 10 #include <fdt_support.h> 11 #include <fsl_dcu_fb.h> 12 #include <linux/fb.h> 13 #include <malloc.h> 14 #include <video_fb.h> 15 #include "videomodes.h" 16 17 /* Convert the X,Y resolution pair into a single number */ 18 #define RESOLUTION(x, y) (((u32)(x) << 16) | (y)) 19 20 #ifdef CONFIG_SYS_FSL_DCU_LE 21 #define dcu_read32 in_le32 22 #define dcu_write32 out_le32 23 #elif defined(CONFIG_SYS_FSL_DCU_BE) 24 #define dcu_read32 in_be32 25 #define dcu_write32 out_be32 26 #endif 27 28 #define DCU_MODE_BLEND_ITER(x) ((x) << 20) 29 #define DCU_MODE_RASTER_EN (1 << 14) 30 #define DCU_MODE_NORMAL 1 31 #define DCU_MODE_COLORBAR 3 32 #define DCU_BGND_R(x) ((x) << 16) 33 #define DCU_BGND_G(x) ((x) << 8) 34 #define DCU_BGND_B(x) (x) 35 #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) 36 #define DCU_DISP_SIZE_DELTA_X(x) (x) 37 #define DCU_HSYN_PARA_BP(x) ((x) << 22) 38 #define DCU_HSYN_PARA_PW(x) ((x) << 11) 39 #define DCU_HSYN_PARA_FP(x) (x) 40 #define DCU_VSYN_PARA_BP(x) ((x) << 22) 41 #define DCU_VSYN_PARA_PW(x) ((x) << 11) 42 #define DCU_VSYN_PARA_FP(x) (x) 43 #define DCU_SYN_POL_INV_PXCK_FALL (1 << 6) 44 #define DCU_SYN_POL_NEG_REMAIN (0 << 5) 45 #define DCU_SYN_POL_INV_VS_LOW (1 << 1) 46 #define DCU_SYN_POL_INV_HS_LOW (1) 47 #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) 48 #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8) 49 #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) 50 #define DCU_UPDATE_MODE_MODE (1 << 31) 51 #define DCU_UPDATE_MODE_READREG (1 << 30) 52 53 #define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16) 54 #define DCU_CTRLDESCLN_1_WIDTH(x) (x) 55 #define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16) 56 #define DCU_CTRLDESCLN_2_POSX(x) (x) 57 #define DCU_CTRLDESCLN_4_EN (1 << 31) 58 #define DCU_CTRLDESCLN_4_TILE_EN (1 << 30) 59 #define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29) 60 #define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28) 61 #define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20) 62 #define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16) 63 #define DCU_CTRLDESCLN_4_RLE_EN (1 << 15) 64 #define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4) 65 #define DCU_CTRLDESCLN_4_BB_ON (1 << 2) 66 #define DCU_CTRLDESCLN_4_AB(x) (x) 67 #define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16) 68 #define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8) 69 #define DCU_CTRLDESCLN_5_CKMAX_B(x) (x) 70 #define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16) 71 #define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8) 72 #define DCU_CTRLDESCLN_6_CKMIN_B(x) (x) 73 #define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16) 74 #define DCU_CTRLDESCLN_7_TILE_HOR(x) (x) 75 #define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x) 76 #define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x) 77 78 #define BPP_16_RGB565 4 79 #define BPP_24_RGB888 5 80 #define BPP_32_ARGB8888 6 81 82 DECLARE_GLOBAL_DATA_PTR; 83 84 /* 85 * This setting is used for the TWR_LCD_RGB card 86 */ 87 static struct fb_videomode fsl_dcu_mode_480_272 = { 88 .name = "480x272-60", 89 .refresh = 60, 90 .xres = 480, 91 .yres = 272, 92 .pixclock = 91996, 93 .left_margin = 2, 94 .right_margin = 2, 95 .upper_margin = 1, 96 .lower_margin = 1, 97 .hsync_len = 41, 98 .vsync_len = 2, 99 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 100 .vmode = FB_VMODE_NONINTERLACED 101 }; 102 103 /* 104 * This setting is used for Siliconimage SiI9022A HDMI 105 */ 106 static struct fb_videomode fsl_dcu_cea_mode_640_480 = { 107 .name = "640x480-60", 108 .refresh = 60, 109 .xres = 640, 110 .yres = 480, 111 .pixclock = 39722, 112 .left_margin = 48, 113 .right_margin = 16, 114 .upper_margin = 33, 115 .lower_margin = 10, 116 .hsync_len = 96, 117 .vsync_len = 2, 118 .sync = 0, 119 .vmode = FB_VMODE_NONINTERLACED, 120 }; 121 122 static struct fb_videomode fsl_dcu_mode_640_480 = { 123 .name = "640x480-60", 124 .refresh = 60, 125 .xres = 640, 126 .yres = 480, 127 .pixclock = 25175, 128 .left_margin = 40, 129 .right_margin = 24, 130 .upper_margin = 32, 131 .lower_margin = 11, 132 .hsync_len = 96, 133 .vsync_len = 2, 134 .sync = 0, 135 .vmode = FB_VMODE_NONINTERLACED, 136 }; 137 138 static struct fb_videomode fsl_dcu_mode_800_480 = { 139 .name = "800x480-60", 140 .refresh = 60, 141 .xres = 800, 142 .yres = 480, 143 .pixclock = 33260, 144 .left_margin = 216, 145 .right_margin = 40, 146 .upper_margin = 35, 147 .lower_margin = 10, 148 .hsync_len = 128, 149 .vsync_len = 2, 150 .sync = 0, 151 .vmode = FB_VMODE_NONINTERLACED, 152 }; 153 154 static struct fb_videomode fsl_dcu_mode_1024_600 = { 155 .name = "1024x600-60", 156 .refresh = 60, 157 .xres = 1024, 158 .yres = 600, 159 .pixclock = 48000, 160 .left_margin = 104, 161 .right_margin = 43, 162 .upper_margin = 24, 163 .lower_margin = 20, 164 .hsync_len = 5, 165 .vsync_len = 5, 166 .sync = 0, 167 .vmode = FB_VMODE_NONINTERLACED, 168 }; 169 170 /* 171 * DCU register map 172 */ 173 struct dcu_reg { 174 u32 desc_cursor[4]; 175 u32 mode; 176 u32 bgnd; 177 u32 disp_size; 178 u32 hsyn_para; 179 u32 vsyn_para; 180 u32 synpol; 181 u32 threshold; 182 u32 int_status; 183 u32 int_mask; 184 u32 colbar[8]; 185 u32 div_ratio; 186 u32 sign_calc[2]; 187 u32 crc_val; 188 u8 res_064[0x6c-0x64]; 189 u32 parr_err_status1; 190 u8 res_070[0x7c-0x70]; 191 u32 parr_err_status3; 192 u32 mparr_err_status1; 193 u8 res_084[0x90-0x84]; 194 u32 mparr_err_status3; 195 u32 threshold_inp_buf[2]; 196 u8 res_09c[0xa0-0x9c]; 197 u32 luma_comp; 198 u32 chroma_red; 199 u32 chroma_green; 200 u32 chroma_blue; 201 u32 crc_pos; 202 u32 lyr_intpol_en; 203 u32 lyr_luma_comp; 204 u32 lyr_chrm_red; 205 u32 lyr_chrm_grn; 206 u32 lyr_chrm_blue; 207 u8 res_0c4[0xcc-0xc8]; 208 u32 update_mode; 209 u32 underrun; 210 u8 res_0d4[0x100-0xd4]; 211 u32 gpr; 212 u32 slr_l[2]; 213 u32 slr_disp_size; 214 u32 slr_hvsync_para; 215 u32 slr_pol; 216 u32 slr_l_transp[2]; 217 u8 res_120[0x200-0x120]; 218 u32 ctrldescl[DCU_LAYER_MAX_NUM][16]; 219 }; 220 221 static struct fb_info info; 222 223 static void reset_total_layers(void) 224 { 225 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; 226 int i; 227 228 for (i = 0; i < DCU_LAYER_MAX_NUM; i++) { 229 dcu_write32(®s->ctrldescl[i][0], 0); 230 dcu_write32(®s->ctrldescl[i][1], 0); 231 dcu_write32(®s->ctrldescl[i][2], 0); 232 dcu_write32(®s->ctrldescl[i][3], 0); 233 dcu_write32(®s->ctrldescl[i][4], 0); 234 dcu_write32(®s->ctrldescl[i][5], 0); 235 dcu_write32(®s->ctrldescl[i][6], 0); 236 dcu_write32(®s->ctrldescl[i][7], 0); 237 dcu_write32(®s->ctrldescl[i][8], 0); 238 dcu_write32(®s->ctrldescl[i][9], 0); 239 dcu_write32(®s->ctrldescl[i][10], 0); 240 } 241 } 242 243 static int layer_ctrldesc_init(int index, u32 pixel_format) 244 { 245 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; 246 unsigned int bpp = BPP_24_RGB888; 247 248 dcu_write32(®s->ctrldescl[index][0], 249 DCU_CTRLDESCLN_1_HEIGHT(info.var.yres) | 250 DCU_CTRLDESCLN_1_WIDTH(info.var.xres)); 251 252 dcu_write32(®s->ctrldescl[index][1], 253 DCU_CTRLDESCLN_2_POSY(0) | 254 DCU_CTRLDESCLN_2_POSX(0)); 255 256 dcu_write32(®s->ctrldescl[index][2], (unsigned int)info.screen_base); 257 258 switch (pixel_format) { 259 case 16: 260 bpp = BPP_16_RGB565; 261 break; 262 case 24: 263 bpp = BPP_24_RGB888; 264 break; 265 case 32: 266 bpp = BPP_32_ARGB8888; 267 break; 268 default: 269 printf("unsupported color depth: %u\n", pixel_format); 270 } 271 272 dcu_write32(®s->ctrldescl[index][3], 273 DCU_CTRLDESCLN_4_EN | 274 DCU_CTRLDESCLN_4_TRANS(0xff) | 275 DCU_CTRLDESCLN_4_BPP(bpp) | 276 DCU_CTRLDESCLN_4_AB(0)); 277 278 dcu_write32(®s->ctrldescl[index][4], 279 DCU_CTRLDESCLN_5_CKMAX_R(0xff) | 280 DCU_CTRLDESCLN_5_CKMAX_G(0xff) | 281 DCU_CTRLDESCLN_5_CKMAX_B(0xff)); 282 dcu_write32(®s->ctrldescl[index][5], 283 DCU_CTRLDESCLN_6_CKMIN_R(0) | 284 DCU_CTRLDESCLN_6_CKMIN_G(0) | 285 DCU_CTRLDESCLN_6_CKMIN_B(0)); 286 287 dcu_write32(®s->ctrldescl[index][6], 288 DCU_CTRLDESCLN_7_TILE_VER(0) | 289 DCU_CTRLDESCLN_7_TILE_HOR(0)); 290 291 dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0)); 292 dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0)); 293 294 return 0; 295 } 296 297 int fsl_dcu_init(unsigned int xres, unsigned int yres, 298 unsigned int pixel_format) 299 { 300 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; 301 unsigned int div, mode; 302 303 info.screen_size = 304 info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8); 305 306 if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) { 307 info.screen_size = 0; 308 return -ENOMEM; 309 } 310 311 /* Reserve framebuffer at the end of memory */ 312 gd->fb_base = gd->bd->bi_dram[0].start + 313 gd->bd->bi_dram[0].size - info.screen_size; 314 info.screen_base = (char *)gd->fb_base; 315 316 memset(info.screen_base, 0, info.screen_size); 317 318 reset_total_layers(); 319 320 dcu_write32(®s->disp_size, 321 DCU_DISP_SIZE_DELTA_Y(info.var.yres) | 322 DCU_DISP_SIZE_DELTA_X(info.var.xres / 16)); 323 324 dcu_write32(®s->hsyn_para, 325 DCU_HSYN_PARA_BP(info.var.left_margin) | 326 DCU_HSYN_PARA_PW(info.var.hsync_len) | 327 DCU_HSYN_PARA_FP(info.var.right_margin)); 328 329 dcu_write32(®s->vsyn_para, 330 DCU_VSYN_PARA_BP(info.var.upper_margin) | 331 DCU_VSYN_PARA_PW(info.var.vsync_len) | 332 DCU_VSYN_PARA_FP(info.var.lower_margin)); 333 334 dcu_write32(®s->synpol, 335 DCU_SYN_POL_INV_PXCK_FALL | 336 DCU_SYN_POL_NEG_REMAIN | 337 DCU_SYN_POL_INV_VS_LOW | 338 DCU_SYN_POL_INV_HS_LOW); 339 340 dcu_write32(®s->bgnd, 341 DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0)); 342 343 dcu_write32(®s->mode, 344 DCU_MODE_BLEND_ITER(2) | 345 DCU_MODE_RASTER_EN); 346 347 dcu_write32(®s->threshold, 348 DCU_THRESHOLD_LS_BF_VS(0x3) | 349 DCU_THRESHOLD_OUT_BUF_HIGH(0x78) | 350 DCU_THRESHOLD_OUT_BUF_LOW(0)); 351 352 mode = dcu_read32(®s->mode); 353 dcu_write32(®s->mode, mode | DCU_MODE_NORMAL); 354 355 layer_ctrldesc_init(0, pixel_format); 356 357 div = dcu_set_pixel_clock(info.var.pixclock); 358 dcu_write32(®s->div_ratio, (div - 1)); 359 360 dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); 361 362 return 0; 363 } 364 365 ulong board_get_usable_ram_top(ulong total_size) 366 { 367 return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB; 368 } 369 370 void *video_hw_init(void) 371 { 372 static GraphicDevice ctfb; 373 const char *options; 374 unsigned int depth = 0, freq = 0; 375 struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272; 376 377 if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq, 378 &options)) 379 return NULL; 380 381 /* Find the monitor port, which is a required option */ 382 if (!options) 383 return NULL; 384 if (strncmp(options, "monitor=", 8) != 0) 385 return NULL; 386 387 switch (RESOLUTION(ctfb.winSizeX, ctfb.winSizeY)) { 388 case RESOLUTION(480, 272): 389 fsl_dcu_mode_db = &fsl_dcu_mode_480_272; 390 break; 391 case RESOLUTION(640, 480): 392 if (!strncmp(options, "monitor=hdmi", 12)) 393 fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480; 394 else 395 fsl_dcu_mode_db = &fsl_dcu_mode_640_480; 396 break; 397 case RESOLUTION(800, 480): 398 fsl_dcu_mode_db = &fsl_dcu_mode_800_480; 399 break; 400 case RESOLUTION(1024, 600): 401 fsl_dcu_mode_db = &fsl_dcu_mode_1024_600; 402 break; 403 default: 404 printf("unsupported resolution %ux%u\n", 405 ctfb.winSizeX, ctfb.winSizeY); 406 } 407 408 info.var.xres = fsl_dcu_mode_db->xres; 409 info.var.yres = fsl_dcu_mode_db->yres; 410 info.var.bits_per_pixel = 32; 411 info.var.pixclock = fsl_dcu_mode_db->pixclock; 412 info.var.left_margin = fsl_dcu_mode_db->left_margin; 413 info.var.right_margin = fsl_dcu_mode_db->right_margin; 414 info.var.upper_margin = fsl_dcu_mode_db->upper_margin; 415 info.var.lower_margin = fsl_dcu_mode_db->lower_margin; 416 info.var.hsync_len = fsl_dcu_mode_db->hsync_len; 417 info.var.vsync_len = fsl_dcu_mode_db->vsync_len; 418 info.var.sync = fsl_dcu_mode_db->sync; 419 info.var.vmode = fsl_dcu_mode_db->vmode; 420 info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8; 421 422 if (platform_dcu_init(ctfb.winSizeX, ctfb.winSizeY, 423 options + 8, fsl_dcu_mode_db) < 0) 424 return NULL; 425 426 ctfb.frameAdrs = (unsigned int)info.screen_base; 427 ctfb.plnSizeX = ctfb.winSizeX; 428 ctfb.plnSizeY = ctfb.winSizeY; 429 430 ctfb.gdfBytesPP = 4; 431 ctfb.gdfIndex = GDF_32BIT_X888RGB; 432 433 ctfb.memSize = info.screen_size; 434 435 return &ctfb; 436 } 437 438 #if defined(CONFIG_OF_BOARD_SETUP) 439 int fsl_dcu_fixedfb_setup(void *blob) 440 { 441 u64 start, size; 442 int ret; 443 444 start = gd->bd->bi_dram[0].start; 445 size = gd->bd->bi_dram[0].size - info.screen_size; 446 447 /* 448 * Align size on section size (1 MiB). 449 */ 450 size &= 0xfff00000; 451 ret = fdt_fixup_memory_banks(blob, &start, &size, 1); 452 if (ret) { 453 eprintf("Cannot setup fb: Error reserving memory\n"); 454 return ret; 455 } 456 457 return 0; 458 } 459 #endif 460
