1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012 4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach (at) gdsys.cc 5 */ 6 7 /* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <errno.h> 12 #include <i2c.h> 13 14 #define DP501_I2C_ADDR 0x08 15 16 #ifdef CONFIG_SYS_DP501_I2C 17 int dp501_i2c[] = CONFIG_SYS_DP501_I2C; 18 #endif 19 20 #ifdef CONFIG_SYS_DP501_BASE 21 int dp501_base[] = CONFIG_SYS_DP501_BASE; 22 #endif 23 24 static void dp501_setbits(u8 addr, u8 reg, u8 mask) 25 { 26 u8 val; 27 28 val = i2c_reg_read(addr, reg); 29 setbits_8(&val, mask); 30 i2c_reg_write(addr, reg, val); 31 } 32 33 static void dp501_clrbits(u8 addr, u8 reg, u8 mask) 34 { 35 u8 val; 36 37 val = i2c_reg_read(addr, reg); 38 clrbits_8(&val, mask); 39 i2c_reg_write(addr, reg, val); 40 } 41 42 static int dp501_detect_cable_adapter(u8 addr) 43 { 44 u8 val = i2c_reg_read(addr, 0x00); 45 46 return !(val & 0x04); 47 } 48 49 static void dp501_link_training(u8 addr) 50 { 51 u8 val; 52 u8 link_bw; 53 u8 max_lane_cnt; 54 u8 lane_cnt; 55 56 val = i2c_reg_read(addr, 0x51); 57 if (val >= 0x0a) 58 link_bw = 0x0a; 59 else 60 link_bw = 0x06; 61 if (link_bw != val) 62 printf("DP sink supports %d Mbps link rate, set to %d Mbps\n", 63 val * 270, link_bw * 270); 64 i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */ 65 val = i2c_reg_read(addr, 0x52); 66 max_lane_cnt = val & 0x1f; 67 if (max_lane_cnt >= 4) 68 lane_cnt = 4; 69 else 70 lane_cnt = max_lane_cnt; 71 if (lane_cnt != max_lane_cnt) 72 printf("DP sink supports %d lanes, set to %d lanes\n", 73 max_lane_cnt, lane_cnt); 74 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ 75 val = i2c_reg_read(addr, 0x53); 76 i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */ 77 78 i2c_reg_write(addr, 0x5f, 0x0d); /* start training */ 79 } 80 81 void dp501_powerup(u8 addr) 82 { 83 dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */ 84 dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/ 85 i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */ 86 dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */ 87 dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */ 88 i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */ 89 dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */ 90 dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */ 91 dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */ 92 93 #ifdef CONFIG_SYS_DP501_VCAPCTRL0 94 i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0); 95 #else 96 i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */ 97 #endif 98 99 #ifdef CONFIG_SYS_DP501_DIFFERENTIAL 100 i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */ 101 i2c_reg_write(addr + 2, 0x25, 0x04); 102 i2c_reg_write(addr + 2, 0x26, 0x10); 103 #else 104 i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */ 105 #endif 106 107 i2c_reg_write(addr + 2, 0x1a, 0x04); /* SPDIF input method TTL */ 108 109 i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */ 110 i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */ 111 i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */ 112 i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */ 113 i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */ 114 i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */ 115 dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */ 116 i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */ 117 i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */ 118 i2c_reg_write(addr, 0x87, 0x7f); /* set retry counter as 7 119 retry interval 400us */ 120 121 if (dp501_detect_cable_adapter(addr)) { 122 printf("DVI/HDMI cable adapter detected\n"); 123 i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */ 124 dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */ 125 } else { 126 printf("no DVI/HDMI cable adapter detected\n"); 127 dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */ 128 129 dp501_link_training(addr); 130 } 131 } 132 133 void dp501_powerdown(u8 addr) 134 { 135 dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */ 136 } 137 138 139 int dp501_probe(unsigned screen, bool power) 140 { 141 #ifdef CONFIG_SYS_DP501_BASE 142 uint8_t dp501_addr = dp501_base[screen]; 143 #else 144 uint8_t dp501_addr = DP501_I2C_ADDR; 145 #endif 146 147 #ifdef CONFIG_SYS_DP501_I2C 148 i2c_set_bus_num(dp501_i2c[screen]); 149 #endif 150 151 if (i2c_probe(dp501_addr)) 152 return -1; 153 154 dp501_powerup(dp501_addr); 155 156 return 0; 157 } 158
