1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi (at) ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy (at) linutronix.de> 9 * 10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported 11 * to uboot. 12 * 13 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA 14 */ 15 16 #include <common.h> 17 #include <malloc.h> 18 #include <dwc3-uboot.h> 19 #include <asm/dma-mapping.h> 20 #include <linux/ioport.h> 21 #include <dm.h> 22 23 #include <linux/usb/ch9.h> 24 #include <linux/usb/gadget.h> 25 26 #include "core.h" 27 #include "gadget.h" 28 #include "io.h" 29 30 #include "linux-compat.h" 31 32 static LIST_HEAD(dwc3_list); 33 /* -------------------------------------------------------------------------- */ 34 35 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 36 { 37 u32 reg; 38 39 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 40 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 41 reg |= DWC3_GCTL_PRTCAPDIR(mode); 42 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 43 } 44 45 /** 46 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 47 * @dwc: pointer to our context structure 48 */ 49 static int dwc3_core_soft_reset(struct dwc3 *dwc) 50 { 51 u32 reg; 52 53 /* Before Resetting PHY, put Core in Reset */ 54 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 55 reg |= DWC3_GCTL_CORESOFTRESET; 56 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 57 58 /* Assert USB3 PHY reset */ 59 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 60 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 61 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 62 63 /* Assert USB2 PHY reset */ 64 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 65 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 66 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 67 68 mdelay(100); 69 70 /* Clear USB3 PHY reset */ 71 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 72 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 73 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 74 75 /* Clear USB2 PHY reset */ 76 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 77 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 78 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 79 80 mdelay(100); 81 82 /* After PHYs are stable we can take Core out of reset state */ 83 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 84 reg &= ~DWC3_GCTL_CORESOFTRESET; 85 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 86 87 return 0; 88 } 89 90 /** 91 * dwc3_free_one_event_buffer - Frees one event buffer 92 * @dwc: Pointer to our controller context structure 93 * @evt: Pointer to event buffer to be freed 94 */ 95 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 96 struct dwc3_event_buffer *evt) 97 { 98 dma_free_coherent(evt->buf); 99 } 100 101 /** 102 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 103 * @dwc: Pointer to our controller context structure 104 * @length: size of the event buffer 105 * 106 * Returns a pointer to the allocated event buffer structure on success 107 * otherwise ERR_PTR(errno). 108 */ 109 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 110 unsigned length) 111 { 112 struct dwc3_event_buffer *evt; 113 114 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt), 115 GFP_KERNEL); 116 if (!evt) 117 return ERR_PTR(-ENOMEM); 118 119 evt->dwc = dwc; 120 evt->length = length; 121 evt->buf = dma_alloc_coherent(length, 122 (unsigned long *)&evt->dma); 123 if (!evt->buf) 124 return ERR_PTR(-ENOMEM); 125 126 dwc3_flush_cache((uintptr_t)evt->buf, evt->length); 127 128 return evt; 129 } 130 131 /** 132 * dwc3_free_event_buffers - frees all allocated event buffers 133 * @dwc: Pointer to our controller context structure 134 */ 135 static void dwc3_free_event_buffers(struct dwc3 *dwc) 136 { 137 struct dwc3_event_buffer *evt; 138 int i; 139 140 for (i = 0; i < dwc->num_event_buffers; i++) { 141 evt = dwc->ev_buffs[i]; 142 if (evt) 143 dwc3_free_one_event_buffer(dwc, evt); 144 } 145 } 146 147 /** 148 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 149 * @dwc: pointer to our controller context structure 150 * @length: size of event buffer 151 * 152 * Returns 0 on success otherwise negative errno. In the error case, dwc 153 * may contain some buffers allocated but not all which were requested. 154 */ 155 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 156 { 157 int num; 158 int i; 159 160 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 161 dwc->num_event_buffers = num; 162 163 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE, 164 sizeof(*dwc->ev_buffs) * num); 165 if (!dwc->ev_buffs) 166 return -ENOMEM; 167 168 for (i = 0; i < num; i++) { 169 struct dwc3_event_buffer *evt; 170 171 evt = dwc3_alloc_one_event_buffer(dwc, length); 172 if (IS_ERR(evt)) { 173 dev_err(dwc->dev, "can't allocate event buffer\n"); 174 return PTR_ERR(evt); 175 } 176 dwc->ev_buffs[i] = evt; 177 } 178 179 return 0; 180 } 181 182 /** 183 * dwc3_event_buffers_setup - setup our allocated event buffers 184 * @dwc: pointer to our controller context structure 185 * 186 * Returns 0 on success otherwise negative errno. 187 */ 188 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 189 { 190 struct dwc3_event_buffer *evt; 191 int n; 192 193 for (n = 0; n < dwc->num_event_buffers; n++) { 194 evt = dwc->ev_buffs[n]; 195 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 196 evt->buf, (unsigned long long) evt->dma, 197 evt->length); 198 199 evt->lpos = 0; 200 201 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 202 lower_32_bits(evt->dma)); 203 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 204 upper_32_bits(evt->dma)); 205 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 206 DWC3_GEVNTSIZ_SIZE(evt->length)); 207 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 208 } 209 210 return 0; 211 } 212 213 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 214 { 215 struct dwc3_event_buffer *evt; 216 int n; 217 218 for (n = 0; n < dwc->num_event_buffers; n++) { 219 evt = dwc->ev_buffs[n]; 220 221 evt->lpos = 0; 222 223 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 224 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 225 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 226 | DWC3_GEVNTSIZ_SIZE(0)); 227 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 228 } 229 } 230 231 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 232 { 233 if (!dwc->has_hibernation) 234 return 0; 235 236 if (!dwc->nr_scratch) 237 return 0; 238 239 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 240 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 241 if (!dwc->scratchbuf) 242 return -ENOMEM; 243 244 return 0; 245 } 246 247 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 248 { 249 dma_addr_t scratch_addr; 250 u32 param; 251 int ret; 252 253 if (!dwc->has_hibernation) 254 return 0; 255 256 if (!dwc->nr_scratch) 257 return 0; 258 259 scratch_addr = dma_map_single(dwc->scratchbuf, 260 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 261 DMA_BIDIRECTIONAL); 262 if (dma_mapping_error(dwc->dev, scratch_addr)) { 263 dev_err(dwc->dev, "failed to map scratch buffer\n"); 264 ret = -EFAULT; 265 goto err0; 266 } 267 268 dwc->scratch_addr = scratch_addr; 269 270 param = lower_32_bits(scratch_addr); 271 272 ret = dwc3_send_gadget_generic_command(dwc, 273 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 274 if (ret < 0) 275 goto err1; 276 277 param = upper_32_bits(scratch_addr); 278 279 ret = dwc3_send_gadget_generic_command(dwc, 280 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 281 if (ret < 0) 282 goto err1; 283 284 return 0; 285 286 err1: 287 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 288 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 289 290 err0: 291 return ret; 292 } 293 294 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 295 { 296 if (!dwc->has_hibernation) 297 return; 298 299 if (!dwc->nr_scratch) 300 return; 301 302 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 303 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 304 kfree(dwc->scratchbuf); 305 } 306 307 static void dwc3_core_num_eps(struct dwc3 *dwc) 308 { 309 struct dwc3_hwparams *parms = &dwc->hwparams; 310 311 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 312 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 313 314 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", 315 dwc->num_in_eps, dwc->num_out_eps); 316 } 317 318 static void dwc3_cache_hwparams(struct dwc3 *dwc) 319 { 320 struct dwc3_hwparams *parms = &dwc->hwparams; 321 322 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 323 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 324 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 325 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 326 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 327 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 328 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 329 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 330 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 331 } 332 333 /** 334 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 335 * @dwc: Pointer to our controller context structure 336 */ 337 static void dwc3_phy_setup(struct dwc3 *dwc) 338 { 339 u32 reg; 340 341 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 342 343 /* 344 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 345 * to '0' during coreConsultant configuration. So default value 346 * will be '0' when the core is reset. Application needs to set it 347 * to '1' after the core initialization is completed. 348 */ 349 if (dwc->revision > DWC3_REVISION_194A) 350 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 351 352 if (dwc->u2ss_inp3_quirk) 353 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 354 355 if (dwc->req_p1p2p3_quirk) 356 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 357 358 if (dwc->del_p1p2p3_quirk) 359 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 360 361 if (dwc->del_phy_power_chg_quirk) 362 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 363 364 if (dwc->lfps_filter_quirk) 365 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 366 367 if (dwc->rx_detect_poll_quirk) 368 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 369 370 if (dwc->tx_de_emphasis_quirk) 371 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 372 373 if (dwc->dis_u3_susphy_quirk) 374 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 375 376 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 377 378 mdelay(100); 379 380 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 381 382 /* 383 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 384 * '0' during coreConsultant configuration. So default value will 385 * be '0' when the core is reset. Application needs to set it to 386 * '1' after the core initialization is completed. 387 */ 388 if (dwc->revision > DWC3_REVISION_194A) 389 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 390 391 if (dwc->dis_u2_susphy_quirk) 392 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 393 394 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 395 396 mdelay(100); 397 } 398 399 /** 400 * dwc3_core_init - Low-level initialization of DWC3 Core 401 * @dwc: Pointer to our controller context structure 402 * 403 * Returns 0 on success otherwise negative errno. 404 */ 405 static int dwc3_core_init(struct dwc3 *dwc) 406 { 407 unsigned long timeout; 408 u32 hwparams4 = dwc->hwparams.hwparams4; 409 u32 reg; 410 int ret; 411 412 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 413 /* This should read as U3 followed by revision number */ 414 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 415 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 416 ret = -ENODEV; 417 goto err0; 418 } 419 dwc->revision = reg; 420 421 /* Handle USB2.0-only core configuration */ 422 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 423 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 424 if (dwc->maximum_speed == USB_SPEED_SUPER) 425 dwc->maximum_speed = USB_SPEED_HIGH; 426 } 427 428 /* issue device SoftReset too */ 429 timeout = 5000; 430 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 431 while (timeout--) { 432 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 433 if (!(reg & DWC3_DCTL_CSFTRST)) 434 break; 435 }; 436 437 if (!timeout) { 438 dev_err(dwc->dev, "Reset Timed Out\n"); 439 ret = -ETIMEDOUT; 440 goto err0; 441 } 442 443 ret = dwc3_core_soft_reset(dwc); 444 if (ret) 445 goto err0; 446 447 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 448 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 449 450 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 451 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 452 /** 453 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 454 * issue which would cause xHCI compliance tests to fail. 455 * 456 * Because of that we cannot enable clock gating on such 457 * configurations. 458 * 459 * Refers to: 460 * 461 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 462 * SOF/ITP Mode Used 463 */ 464 if ((dwc->dr_mode == USB_DR_MODE_HOST || 465 dwc->dr_mode == USB_DR_MODE_OTG) && 466 (dwc->revision >= DWC3_REVISION_210A && 467 dwc->revision <= DWC3_REVISION_250A)) 468 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 469 else 470 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 471 break; 472 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 473 /* enable hibernation here */ 474 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 475 476 /* 477 * REVISIT Enabling this bit so that host-mode hibernation 478 * will work. Device-mode hibernation is not yet implemented. 479 */ 480 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 481 break; 482 default: 483 dev_dbg(dwc->dev, "No power optimization available\n"); 484 } 485 486 /* check if current dwc3 is on simulation board */ 487 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 488 dev_dbg(dwc->dev, "it is on FPGA board\n"); 489 dwc->is_fpga = true; 490 } 491 492 if(dwc->disable_scramble_quirk && !dwc->is_fpga) 493 WARN(true, 494 "disable_scramble cannot be used on non-FPGA builds\n"); 495 496 if (dwc->disable_scramble_quirk && dwc->is_fpga) 497 reg |= DWC3_GCTL_DISSCRAMBLE; 498 else 499 reg &= ~DWC3_GCTL_DISSCRAMBLE; 500 501 if (dwc->u2exit_lfps_quirk) 502 reg |= DWC3_GCTL_U2EXIT_LFPS; 503 504 /* 505 * WORKAROUND: DWC3 revisions <1.90a have a bug 506 * where the device can fail to connect at SuperSpeed 507 * and falls back to high-speed mode which causes 508 * the device to enter a Connect/Disconnect loop 509 */ 510 if (dwc->revision < DWC3_REVISION_190A) 511 reg |= DWC3_GCTL_U2RSTECN; 512 513 dwc3_core_num_eps(dwc); 514 515 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 516 517 dwc3_phy_setup(dwc); 518 519 ret = dwc3_alloc_scratch_buffers(dwc); 520 if (ret) 521 goto err0; 522 523 ret = dwc3_setup_scratch_buffers(dwc); 524 if (ret) 525 goto err1; 526 527 return 0; 528 529 err1: 530 dwc3_free_scratch_buffers(dwc); 531 532 err0: 533 return ret; 534 } 535 536 static void dwc3_core_exit(struct dwc3 *dwc) 537 { 538 dwc3_free_scratch_buffers(dwc); 539 } 540 541 static int dwc3_core_init_mode(struct dwc3 *dwc) 542 { 543 int ret; 544 545 switch (dwc->dr_mode) { 546 case USB_DR_MODE_PERIPHERAL: 547 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 548 ret = dwc3_gadget_init(dwc); 549 if (ret) { 550 dev_err(dev, "failed to initialize gadget\n"); 551 return ret; 552 } 553 break; 554 case USB_DR_MODE_HOST: 555 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 556 ret = dwc3_host_init(dwc); 557 if (ret) { 558 dev_err(dev, "failed to initialize host\n"); 559 return ret; 560 } 561 break; 562 case USB_DR_MODE_OTG: 563 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 564 ret = dwc3_host_init(dwc); 565 if (ret) { 566 dev_err(dev, "failed to initialize host\n"); 567 return ret; 568 } 569 570 ret = dwc3_gadget_init(dwc); 571 if (ret) { 572 dev_err(dev, "failed to initialize gadget\n"); 573 return ret; 574 } 575 break; 576 default: 577 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 578 return -EINVAL; 579 } 580 581 return 0; 582 } 583 584 static void dwc3_core_exit_mode(struct dwc3 *dwc) 585 { 586 switch (dwc->dr_mode) { 587 case USB_DR_MODE_PERIPHERAL: 588 dwc3_gadget_exit(dwc); 589 break; 590 case USB_DR_MODE_HOST: 591 dwc3_host_exit(dwc); 592 break; 593 case USB_DR_MODE_OTG: 594 dwc3_host_exit(dwc); 595 dwc3_gadget_exit(dwc); 596 break; 597 default: 598 /* do nothing */ 599 break; 600 } 601 } 602 603 #define DWC3_ALIGN_MASK (16 - 1) 604 605 /** 606 * dwc3_uboot_init - dwc3 core uboot initialization code 607 * @dwc3_dev: struct dwc3_device containing initialization data 608 * 609 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux 610 * kernel driver). Pointer to dwc3_device should be passed containing 611 * base address and other initialization data. Returns '0' on success and 612 * a negative value on failure. 613 * 614 * Generally called from board_usb_init() implemented in board file. 615 */ 616 int dwc3_uboot_init(struct dwc3_device *dwc3_dev) 617 { 618 struct dwc3 *dwc; 619 struct device *dev = NULL; 620 u8 lpm_nyet_threshold; 621 u8 tx_de_emphasis; 622 u8 hird_threshold; 623 624 int ret; 625 626 void *mem; 627 628 mem = devm_kzalloc((struct udevice *)dev, 629 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 630 if (!mem) 631 return -ENOMEM; 632 633 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 634 dwc->mem = mem; 635 636 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base + 637 DWC3_GLOBALS_REGS_START); 638 639 /* default to highest possible threshold */ 640 lpm_nyet_threshold = 0xff; 641 642 /* default to -3.5dB de-emphasis */ 643 tx_de_emphasis = 1; 644 645 /* 646 * default to assert utmi_sleep_n and use maximum allowed HIRD 647 * threshold value of 0b1100 648 */ 649 hird_threshold = 12; 650 651 dwc->maximum_speed = dwc3_dev->maximum_speed; 652 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum; 653 if (dwc3_dev->lpm_nyet_threshold) 654 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold; 655 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend; 656 if (dwc3_dev->hird_threshold) 657 hird_threshold = dwc3_dev->hird_threshold; 658 659 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize; 660 dwc->dr_mode = dwc3_dev->dr_mode; 661 662 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk; 663 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk; 664 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk; 665 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk; 666 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk; 667 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk; 668 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk; 669 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk; 670 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; 671 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; 672 673 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; 674 if (dwc3_dev->tx_de_emphasis) 675 tx_de_emphasis = dwc3_dev->tx_de_emphasis; 676 677 /* default to superspeed if no maximum_speed passed */ 678 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 679 dwc->maximum_speed = USB_SPEED_SUPER; 680 681 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 682 dwc->tx_de_emphasis = tx_de_emphasis; 683 684 dwc->hird_threshold = hird_threshold 685 | (dwc->is_utmi_l1_suspend << 4); 686 687 dwc->index = dwc3_dev->index; 688 689 dwc3_cache_hwparams(dwc); 690 691 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 692 if (ret) { 693 dev_err(dwc->dev, "failed to allocate event buffers\n"); 694 return -ENOMEM; 695 } 696 697 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 698 dwc->dr_mode = USB_DR_MODE_HOST; 699 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 700 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 701 702 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 703 dwc->dr_mode = USB_DR_MODE_OTG; 704 705 ret = dwc3_core_init(dwc); 706 if (ret) { 707 dev_err(dev, "failed to initialize core\n"); 708 goto err0; 709 } 710 711 ret = dwc3_event_buffers_setup(dwc); 712 if (ret) { 713 dev_err(dwc->dev, "failed to setup event buffers\n"); 714 goto err1; 715 } 716 717 ret = dwc3_core_init_mode(dwc); 718 if (ret) 719 goto err2; 720 721 list_add_tail(&dwc->list, &dwc3_list); 722 723 return 0; 724 725 err2: 726 dwc3_event_buffers_cleanup(dwc); 727 728 err1: 729 dwc3_core_exit(dwc); 730 731 err0: 732 dwc3_free_event_buffers(dwc); 733 734 return ret; 735 } 736 737 /** 738 * dwc3_uboot_exit - dwc3 core uboot cleanup code 739 * @index: index of this controller 740 * 741 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc 742 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller 743 * should be passed and should match with the index passed in 744 * dwc3_device during init. 745 * 746 * Generally called from board file. 747 */ 748 void dwc3_uboot_exit(int index) 749 { 750 struct dwc3 *dwc; 751 752 list_for_each_entry(dwc, &dwc3_list, list) { 753 if (dwc->index != index) 754 continue; 755 756 dwc3_core_exit_mode(dwc); 757 dwc3_event_buffers_cleanup(dwc); 758 dwc3_free_event_buffers(dwc); 759 dwc3_core_exit(dwc); 760 list_del(&dwc->list); 761 kfree(dwc->mem); 762 break; 763 } 764 } 765 766 /** 767 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt 768 * @index: index of this controller 769 * 770 * Invokes dwc3 gadget interrupts. 771 * 772 * Generally called from board file. 773 */ 774 void dwc3_uboot_handle_interrupt(int index) 775 { 776 struct dwc3 *dwc = NULL; 777 778 list_for_each_entry(dwc, &dwc3_list, list) { 779 if (dwc->index != index) 780 continue; 781 782 dwc3_gadget_uboot_handle_interrupt(dwc); 783 break; 784 } 785 } 786 787 MODULE_ALIAS("platform:dwc3"); 788 MODULE_AUTHOR("Felipe Balbi <balbi (at) ti.com>"); 789 MODULE_LICENSE("GPL v2"); 790 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 791 792 #ifdef CONFIG_DM_USB 793 794 int dwc3_init(struct dwc3 *dwc) 795 { 796 int ret; 797 798 dwc3_cache_hwparams(dwc); 799 800 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 801 if (ret) { 802 dev_err(dwc->dev, "failed to allocate event buffers\n"); 803 return -ENOMEM; 804 } 805 806 ret = dwc3_core_init(dwc); 807 if (ret) { 808 dev_err(dev, "failed to initialize core\n"); 809 goto core_fail; 810 } 811 812 ret = dwc3_event_buffers_setup(dwc); 813 if (ret) { 814 dev_err(dwc->dev, "failed to setup event buffers\n"); 815 goto event_fail; 816 } 817 818 ret = dwc3_core_init_mode(dwc); 819 if (ret) 820 goto mode_fail; 821 822 return 0; 823 824 mode_fail: 825 dwc3_event_buffers_cleanup(dwc); 826 827 event_fail: 828 dwc3_core_exit(dwc); 829 830 core_fail: 831 dwc3_free_event_buffers(dwc); 832 833 return ret; 834 } 835 836 void dwc3_remove(struct dwc3 *dwc) 837 { 838 dwc3_core_exit_mode(dwc); 839 dwc3_event_buffers_cleanup(dwc); 840 dwc3_free_event_buffers(dwc); 841 dwc3_core_exit(dwc); 842 kfree(dwc->mem); 843 } 844 845 #endif 846
