1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012 Samsung Electronics 4 * 5 * Author: InKi Dae <inki.dae (at) samsung.com> 6 * Author: Donghwa Lee <dh09.lee (at) samsung.com> 7 */ 8 9 #include <common.h> 10 #include <asm/arch/dsim.h> 11 #include <asm/arch/mipi_dsim.h> 12 #include <asm/arch/power.h> 13 #include <asm/arch/cpu.h> 14 15 #include "exynos_mipi_dsi_lowlevel.h" 16 #include "exynos_mipi_dsi_common.h" 17 18 void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim) 19 { 20 unsigned int reg; 21 22 struct exynos_mipi_dsim *mipi_dsim = 23 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 24 25 reg = readl(&mipi_dsim->swrst); 26 27 reg |= DSIM_FUNCRST; 28 29 writel(reg, &mipi_dsim->swrst); 30 } 31 32 void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim) 33 { 34 unsigned int reg = 0; 35 36 struct exynos_mipi_dsim *mipi_dsim = 37 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 38 39 reg = readl(&mipi_dsim->swrst); 40 41 reg |= DSIM_SWRST; 42 reg |= DSIM_FUNCRST; 43 44 writel(reg, &mipi_dsim->swrst); 45 } 46 47 void exynos_mipi_dsi_sw_release(struct mipi_dsim_device *dsim) 48 { 49 struct exynos_mipi_dsim *mipi_dsim = 50 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 51 unsigned int reg = readl(&mipi_dsim->intsrc); 52 53 reg |= INTSRC_SWRST_RELEASE; 54 55 writel(reg, &mipi_dsim->intsrc); 56 } 57 58 void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim, 59 unsigned int mode, unsigned int mask) 60 { 61 struct exynos_mipi_dsim *mipi_dsim = 62 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 63 unsigned int reg = readl(&mipi_dsim->intmsk); 64 65 if (mask) 66 reg |= mode; 67 else 68 reg &= ~mode; 69 70 writel(reg, &mipi_dsim->intmsk); 71 } 72 73 void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim, 74 unsigned int cfg) 75 { 76 unsigned int reg; 77 struct exynos_mipi_dsim *mipi_dsim = 78 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 79 80 reg = readl(&mipi_dsim->fifoctrl); 81 82 writel(reg & ~(cfg), &mipi_dsim->fifoctrl); 83 udelay(10 * 1000); 84 reg |= cfg; 85 86 writel(reg, &mipi_dsim->fifoctrl); 87 } 88 89 /* 90 * this function set PLL P, M and S value in D-PHY 91 */ 92 void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, 93 unsigned int value) 94 { 95 struct exynos_mipi_dsim *mipi_dsim = 96 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 97 98 writel(DSIM_AFC_CTL(value), &mipi_dsim->phyacchr); 99 } 100 101 void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim, 102 unsigned int width_resol, unsigned int height_resol) 103 { 104 unsigned int reg; 105 struct exynos_mipi_dsim *mipi_dsim = 106 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 107 108 /* standby should be set after configuration so set to not ready*/ 109 reg = (readl(&mipi_dsim->mdresol)) & ~(DSIM_MAIN_STAND_BY); 110 writel(reg, &mipi_dsim->mdresol); 111 112 /* reset resolution */ 113 reg &= ~(DSIM_MAIN_VRESOL(0x7ff) | DSIM_MAIN_HRESOL(0x7ff)); 114 reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol); 115 116 reg |= DSIM_MAIN_STAND_BY; 117 writel(reg, &mipi_dsim->mdresol); 118 } 119 120 void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim, 121 unsigned int cmd_allow, unsigned int vfront, unsigned int vback) 122 { 123 unsigned int reg; 124 struct exynos_mipi_dsim *mipi_dsim = 125 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 126 127 reg = (readl(&mipi_dsim->mvporch)) & 128 ~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) | 129 (DSIM_MAIN_VBP_MASK)); 130 131 reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) | 132 ((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) | 133 ((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT); 134 135 writel(reg, &mipi_dsim->mvporch); 136 } 137 138 void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim, 139 unsigned int front, unsigned int back) 140 { 141 unsigned int reg; 142 struct exynos_mipi_dsim *mipi_dsim = 143 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 144 145 reg = (readl(&mipi_dsim->mhporch)) & 146 ~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK)); 147 148 reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT); 149 150 writel(reg, &mipi_dsim->mhporch); 151 } 152 153 void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim, 154 unsigned int vert, unsigned int hori) 155 { 156 unsigned int reg; 157 struct exynos_mipi_dsim *mipi_dsim = 158 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 159 160 reg = (readl(&mipi_dsim->msync)) & 161 ~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK)); 162 163 reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) | 164 (hori << DSIM_MAIN_HSA_SHIFT); 165 166 writel(reg, &mipi_dsim->msync); 167 } 168 169 void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim, 170 unsigned int vert, unsigned int hori) 171 { 172 unsigned int reg; 173 struct exynos_mipi_dsim *mipi_dsim = 174 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 175 176 reg = (readl(&mipi_dsim->sdresol)) & 177 ~(DSIM_SUB_STANDY_MASK); 178 179 writel(reg, &mipi_dsim->sdresol); 180 181 reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK); 182 reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) | 183 ((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT); 184 writel(reg, &mipi_dsim->sdresol); 185 186 /* DSIM STANDBY */ 187 reg |= (1 << DSIM_SUB_STANDY_SHIFT); 188 writel(reg, &mipi_dsim->sdresol); 189 } 190 191 void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim) 192 { 193 struct mipi_dsim_config *dsim_config = dsim->dsim_config; 194 struct exynos_mipi_dsim *mipi_dsim = 195 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 196 unsigned int cfg = (readl(&mipi_dsim->config)) & 197 ~((1 << DSIM_EOT_PACKET_SHIFT) | 198 (0x1f << DSIM_HSA_MODE_SHIFT) | 199 (0x3 << DSIM_NUM_OF_DATALANE_SHIFT)); 200 201 cfg |= (dsim_config->auto_flush << DSIM_AUTO_FLUSH_SHIFT) | 202 (dsim_config->eot_disable << DSIM_EOT_PACKET_SHIFT) | 203 (dsim_config->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) | 204 (dsim_config->hse << DSIM_HSE_MODE_SHIFT) | 205 (dsim_config->hfp << DSIM_HFP_MODE_SHIFT) | 206 (dsim_config->hbp << DSIM_HBP_MODE_SHIFT) | 207 (dsim_config->hsa << DSIM_HSA_MODE_SHIFT) | 208 (dsim_config->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT); 209 210 writel(cfg, &mipi_dsim->config); 211 } 212 213 void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim, 214 struct mipi_dsim_config *dsim_config) 215 { 216 struct exynos_mipi_dsim *mipi_dsim = 217 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 218 219 u32 reg = (readl(&mipi_dsim->config)) & 220 ~((0x3 << DSIM_BURST_MODE_SHIFT) | (1 << DSIM_VIDEO_MODE_SHIFT) 221 | (0x3 << DSIM_MAINVC_SHIFT) | (0x7 << DSIM_MAINPIX_SHIFT) 222 | (0x3 << DSIM_SUBVC_SHIFT) | (0x7 << DSIM_SUBPIX_SHIFT)); 223 224 if (dsim_config->e_interface == DSIM_VIDEO) 225 reg |= (1 << DSIM_VIDEO_MODE_SHIFT); 226 else if (dsim_config->e_interface == DSIM_COMMAND) 227 reg &= ~(1 << DSIM_VIDEO_MODE_SHIFT); 228 else { 229 printf("unknown lcd type.\n"); 230 return; 231 } 232 233 /* main lcd */ 234 reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << DSIM_BURST_MODE_SHIFT 235 | ((u8) (dsim_config->e_virtual_ch) & 0x3) << DSIM_MAINVC_SHIFT 236 | ((u8) (dsim_config->e_pixel_format) & 0x7) << DSIM_MAINPIX_SHIFT; 237 238 writel(reg, &mipi_dsim->config); 239 } 240 241 void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, 242 unsigned int lane, unsigned int enable) 243 { 244 unsigned int reg; 245 struct exynos_mipi_dsim *mipi_dsim = 246 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 247 248 reg = readl(&mipi_dsim->config); 249 250 if (enable) 251 reg |= DSIM_LANE_ENx(lane); 252 else 253 reg &= ~DSIM_LANE_ENx(lane); 254 255 writel(reg, &mipi_dsim->config); 256 } 257 258 void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim, 259 unsigned int count) 260 { 261 unsigned int cfg; 262 struct exynos_mipi_dsim *mipi_dsim = 263 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 264 265 /* get the data lane number. */ 266 cfg = DSIM_NUM_OF_DATA_LANE(count); 267 268 writel(cfg, &mipi_dsim->config); 269 } 270 271 void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, 272 unsigned int enable, unsigned int afc_code) 273 { 274 struct exynos_mipi_dsim *mipi_dsim = 275 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 276 unsigned int reg = readl(&mipi_dsim->phyacchr); 277 278 reg = 0; 279 280 if (enable) { 281 reg |= DSIM_AFC_EN; 282 reg &= ~(0x7 << DSIM_AFC_CTL_SHIFT); 283 reg |= DSIM_AFC_CTL(afc_code); 284 } else 285 reg &= ~DSIM_AFC_EN; 286 287 writel(reg, &mipi_dsim->phyacchr); 288 } 289 290 void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim, 291 unsigned int enable) 292 { 293 struct exynos_mipi_dsim *mipi_dsim = 294 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 295 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & 296 ~(DSIM_PLL_BYPASS_EXTERNAL); 297 298 reg |= enable << DSIM_PLL_BYPASS_SHIFT; 299 300 writel(reg, &mipi_dsim->clkctrl); 301 } 302 303 void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim, 304 unsigned int freq_band) 305 { 306 struct exynos_mipi_dsim *mipi_dsim = 307 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 308 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & 309 ~(0x1f << DSIM_FREQ_BAND_SHIFT); 310 311 reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT); 312 313 writel(reg, &mipi_dsim->pllctrl); 314 } 315 316 void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim, 317 unsigned int pre_divider, unsigned int main_divider, 318 unsigned int scaler) 319 { 320 struct exynos_mipi_dsim *mipi_dsim = 321 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 322 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & 323 ~(0x7ffff << 1); 324 325 reg |= ((pre_divider & 0x3f) << DSIM_PREDIV_SHIFT) | 326 ((main_divider & 0x1ff) << DSIM_MAIN_SHIFT) | 327 ((scaler & 0x7) << DSIM_SCALER_SHIFT); 328 329 writel(reg, &mipi_dsim->pllctrl); 330 } 331 332 void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim, 333 unsigned int lock_time) 334 { 335 struct exynos_mipi_dsim *mipi_dsim = 336 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 337 338 writel(lock_time, &mipi_dsim->plltmr); 339 } 340 341 void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, 342 unsigned int enable) 343 { 344 struct exynos_mipi_dsim *mipi_dsim = 345 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 346 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & 347 ~(0x1 << DSIM_PLL_EN_SHIFT); 348 349 reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT); 350 351 writel(reg, &mipi_dsim->pllctrl); 352 } 353 354 void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim, 355 unsigned int src) 356 { 357 struct exynos_mipi_dsim *mipi_dsim = 358 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 359 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & 360 ~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT); 361 362 reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT; 363 364 writel(reg, &mipi_dsim->clkctrl); 365 } 366 367 void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim, 368 unsigned int enable) 369 { 370 struct exynos_mipi_dsim *mipi_dsim = 371 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 372 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & 373 ~(1 << DSIM_BYTE_CLKEN_SHIFT); 374 375 reg |= enable << DSIM_BYTE_CLKEN_SHIFT; 376 377 writel(reg, &mipi_dsim->clkctrl); 378 } 379 380 void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim, 381 unsigned int enable, unsigned int prs_val) 382 { 383 struct exynos_mipi_dsim *mipi_dsim = 384 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 385 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & 386 ~((1 << DSIM_ESC_CLKEN_SHIFT) | (0xffff)); 387 388 reg |= enable << DSIM_ESC_CLKEN_SHIFT; 389 if (enable) 390 reg |= prs_val; 391 392 writel(reg, &mipi_dsim->clkctrl); 393 } 394 395 void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim, 396 unsigned int lane_sel, unsigned int enable) 397 { 398 struct exynos_mipi_dsim *mipi_dsim = 399 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 400 unsigned int reg = readl(&mipi_dsim->clkctrl); 401 402 if (enable) 403 reg |= DSIM_LANE_ESC_CLKEN(lane_sel); 404 else 405 reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel); 406 407 writel(reg, &mipi_dsim->clkctrl); 408 } 409 410 void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim, 411 unsigned int enable) 412 { 413 struct exynos_mipi_dsim *mipi_dsim = 414 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 415 unsigned int reg = (readl(&mipi_dsim->escmode)) & 416 ~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT); 417 418 reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT); 419 420 writel(reg, &mipi_dsim->escmode); 421 } 422 423 unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim) 424 { 425 struct exynos_mipi_dsim *mipi_dsim = 426 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 427 unsigned int reg = readl(&mipi_dsim->status); 428 429 /** 430 * check clock and data lane states. 431 * if MIPI-DSI controller was enabled at bootloader then 432 * TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK. 433 * so it should be checked for two case. 434 */ 435 if ((reg & DSIM_STOP_STATE_DAT(0xf)) && 436 ((reg & DSIM_STOP_STATE_CLK) || 437 (reg & DSIM_TX_READY_HS_CLK))) 438 return 1; 439 else 440 return 0; 441 } 442 443 void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim, 444 unsigned int cnt_val) 445 { 446 struct exynos_mipi_dsim *mipi_dsim = 447 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 448 unsigned int reg = (readl(&mipi_dsim->escmode)) & 449 ~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT); 450 451 reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT); 452 453 writel(reg, &mipi_dsim->escmode); 454 } 455 456 void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim, 457 unsigned int timeout) 458 { 459 struct exynos_mipi_dsim *mipi_dsim = 460 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 461 unsigned int reg = (readl(&mipi_dsim->timeout)) & 462 ~(0xff << DSIM_BTA_TOUT_SHIFT); 463 464 reg |= (timeout << DSIM_BTA_TOUT_SHIFT); 465 466 writel(reg, &mipi_dsim->timeout); 467 } 468 469 void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim, 470 unsigned int timeout) 471 { 472 struct exynos_mipi_dsim *mipi_dsim = 473 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 474 unsigned int reg = (readl(&mipi_dsim->timeout)) & 475 ~(0xffff << DSIM_LPDR_TOUT_SHIFT); 476 477 reg |= (timeout << DSIM_LPDR_TOUT_SHIFT); 478 479 writel(reg, &mipi_dsim->timeout); 480 } 481 482 void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim, 483 unsigned int lp) 484 { 485 struct exynos_mipi_dsim *mipi_dsim = 486 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 487 unsigned int reg = readl(&mipi_dsim->escmode); 488 489 reg &= ~DSIM_CMD_LPDT_LP; 490 491 if (lp) 492 reg |= DSIM_CMD_LPDT_LP; 493 494 writel(reg, &mipi_dsim->escmode); 495 } 496 497 void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim, 498 unsigned int lp) 499 { 500 struct exynos_mipi_dsim *mipi_dsim = 501 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 502 unsigned int reg = readl(&mipi_dsim->escmode); 503 504 reg &= ~DSIM_TX_LPDT_LP; 505 506 if (lp) 507 reg |= DSIM_TX_LPDT_LP; 508 509 writel(reg, &mipi_dsim->escmode); 510 } 511 512 void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim, 513 unsigned int enable) 514 { 515 struct exynos_mipi_dsim *mipi_dsim = 516 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 517 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & 518 ~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT); 519 520 reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT; 521 522 writel(reg, &mipi_dsim->clkctrl); 523 } 524 525 void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim, 526 unsigned int swap_en) 527 { 528 struct exynos_mipi_dsim *mipi_dsim = 529 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 530 unsigned int reg = readl(&mipi_dsim->phyacchr1); 531 532 reg &= ~(0x3 << DSIM_DPDN_SWAP_DATA_SHIFT); 533 reg |= (swap_en & 0x3) << DSIM_DPDN_SWAP_DATA_SHIFT; 534 535 writel(reg, &mipi_dsim->phyacchr1); 536 } 537 538 void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim, 539 unsigned int hs_zero) 540 { 541 struct exynos_mipi_dsim *mipi_dsim = 542 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 543 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & 544 ~(0xf << DSIM_ZEROCTRL_SHIFT); 545 546 reg |= ((hs_zero & 0xf) << DSIM_ZEROCTRL_SHIFT); 547 548 writel(reg, &mipi_dsim->pllctrl); 549 } 550 551 void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep) 552 { 553 struct exynos_mipi_dsim *mipi_dsim = 554 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 555 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & 556 ~(0x7 << DSIM_PRECTRL_SHIFT); 557 558 reg |= ((prep & 0x7) << DSIM_PRECTRL_SHIFT); 559 560 writel(reg, &mipi_dsim->pllctrl); 561 } 562 563 void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim) 564 { 565 struct exynos_mipi_dsim *mipi_dsim = 566 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 567 unsigned int reg = readl(&mipi_dsim->intsrc); 568 569 reg |= INTSRC_PLL_STABLE; 570 571 writel(reg, &mipi_dsim->intsrc); 572 } 573 574 void exynos_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim) 575 { 576 struct exynos_mipi_dsim *mipi_dsim = 577 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 578 579 writel(0xffffffff, &mipi_dsim->intsrc); 580 } 581 582 unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim) 583 { 584 unsigned int reg; 585 struct exynos_mipi_dsim *mipi_dsim = 586 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 587 588 reg = readl(&mipi_dsim->status); 589 590 return reg & DSIM_PLL_STABLE ? 1 : 0; 591 } 592 593 unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim) 594 { 595 struct exynos_mipi_dsim *mipi_dsim = 596 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 597 598 return readl(&mipi_dsim->fifoctrl) & ~(0x1f); 599 } 600 601 void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, 602 unsigned int di, const unsigned char data0, const unsigned char data1) 603 { 604 struct exynos_mipi_dsim *mipi_dsim = 605 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 606 unsigned int reg = (DSIM_PKTHDR_DAT1(data1) | DSIM_PKTHDR_DAT0(data0) | 607 DSIM_PKTHDR_DI(di)); 608 609 writel(reg, &mipi_dsim->pkthdr); 610 } 611 612 unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device 613 *dsim) 614 { 615 struct exynos_mipi_dsim *mipi_dsim = 616 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 617 unsigned int reg = readl(&mipi_dsim->intsrc); 618 619 return (reg & INTSRC_FRAME_DONE) ? 1 : 0; 620 } 621 622 void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim) 623 { 624 struct exynos_mipi_dsim *mipi_dsim = 625 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 626 unsigned int reg = readl(&mipi_dsim->intsrc); 627 628 writel(reg | INTSRC_FRAME_DONE, &mipi_dsim->intsrc); 629 } 630 631 void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim, 632 unsigned int tx_data) 633 { 634 struct exynos_mipi_dsim *mipi_dsim = 635 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 636 637 writel(tx_data, &mipi_dsim->payload); 638 } 639
