1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ 2 3 /* 4 * Copyright (C) 2012 Rob Clark <robclark (at) freedesktop.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Rob Clark <robclark (at) freedesktop.org> 27 */ 28 29 30 #include "pipe/p_defines.h" 31 #include "pipe/p_screen.h" 32 #include "pipe/p_state.h" 33 34 #include "util/u_memory.h" 35 #include "util/u_inlines.h" 36 #include "util/u_format.h" 37 #include "util/u_format_s3tc.h" 38 #include "util/u_string.h" 39 #include "util/u_debug.h" 40 41 #include "util/os_time.h" 42 43 #include <stdio.h> 44 #include <errno.h> 45 #include <stdlib.h> 46 47 #include "freedreno_screen.h" 48 #include "freedreno_resource.h" 49 #include "freedreno_fence.h" 50 #include "freedreno_query.h" 51 #include "freedreno_util.h" 52 53 #include "a2xx/fd2_screen.h" 54 #include "a3xx/fd3_screen.h" 55 #include "a4xx/fd4_screen.h" 56 #include "a5xx/fd5_screen.h" 57 58 #include "ir3/ir3_nir.h" 59 60 /* XXX this should go away */ 61 #include "state_tracker/drm_driver.h" 62 63 static const struct debug_named_value debug_options[] = { 64 {"msgs", FD_DBG_MSGS, "Print debug messages"}, 65 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"}, 66 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"}, 67 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"}, 68 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"}, 69 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"}, 70 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"}, 71 {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"}, 72 {"nobin", FD_DBG_NOBIN, "Disable hw binning"}, 73 {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizer debug messages"}, 74 {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"}, 75 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"}, 76 {"flush", FD_DBG_FLUSH, "Force flush after every draw"}, 77 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"}, 78 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"}, 79 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"}, 80 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"}, 81 {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx+)"}, 82 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"}, 83 {"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"}, 84 {"hiprio", FD_DBG_HIPRIO, "Force high-priority context"}, 85 {"ttile", FD_DBG_TTILE, "Enable texture tiling (a5xx)"}, 86 DEBUG_NAMED_VALUE_END 87 }; 88 89 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0) 90 91 int fd_mesa_debug = 0; 92 bool fd_binning_enabled = true; 93 static bool glsl120 = false; 94 95 static const char * 96 fd_screen_get_name(struct pipe_screen *pscreen) 97 { 98 static char buffer[128]; 99 util_snprintf(buffer, sizeof(buffer), "FD%03d", 100 fd_screen(pscreen)->device_id); 101 return buffer; 102 } 103 104 static const char * 105 fd_screen_get_vendor(struct pipe_screen *pscreen) 106 { 107 return "freedreno"; 108 } 109 110 static const char * 111 fd_screen_get_device_vendor(struct pipe_screen *pscreen) 112 { 113 return "Qualcomm"; 114 } 115 116 117 static uint64_t 118 fd_screen_get_timestamp(struct pipe_screen *pscreen) 119 { 120 struct fd_screen *screen = fd_screen(pscreen); 121 122 if (screen->has_timestamp) { 123 uint64_t n; 124 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n); 125 debug_assert(screen->max_freq > 0); 126 return n * 1000000000 / screen->max_freq; 127 } else { 128 int64_t cpu_time = os_time_get() * 1000; 129 return cpu_time + screen->cpu_gpu_time_delta; 130 } 131 132 } 133 134 static void 135 fd_screen_destroy(struct pipe_screen *pscreen) 136 { 137 struct fd_screen *screen = fd_screen(pscreen); 138 139 if (screen->pipe) 140 fd_pipe_del(screen->pipe); 141 142 if (screen->dev) 143 fd_device_del(screen->dev); 144 145 fd_bc_fini(&screen->batch_cache); 146 147 slab_destroy_parent(&screen->transfer_pool); 148 149 mtx_destroy(&screen->lock); 150 151 ralloc_free(screen->compiler); 152 153 free(screen); 154 } 155 156 /* 157 TODO either move caps to a2xx/a3xx specific code, or maybe have some 158 tables for things that differ if the delta is not too much.. 159 */ 160 static int 161 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 162 { 163 struct fd_screen *screen = fd_screen(pscreen); 164 165 /* this is probably not totally correct.. but it's a start: */ 166 switch (param) { 167 /* Supported features (boolean caps). */ 168 case PIPE_CAP_NPOT_TEXTURES: 169 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: 170 case PIPE_CAP_ANISOTROPIC_FILTER: 171 case PIPE_CAP_POINT_SPRITE: 172 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 173 case PIPE_CAP_TEXTURE_SWIZZLE: 174 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 175 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 176 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 177 case PIPE_CAP_SEAMLESS_CUBE_MAP: 178 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 179 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 180 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 181 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 182 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 183 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: 184 case PIPE_CAP_STRING_MARKER: 185 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 186 case PIPE_CAP_TEXTURE_BARRIER: 187 case PIPE_CAP_INVALIDATE_BUFFER: 188 return 1; 189 190 case PIPE_CAP_VERTEXID_NOBASE: 191 return is_a3xx(screen) || is_a4xx(screen); 192 193 case PIPE_CAP_COMPUTE: 194 return has_compute(screen); 195 196 case PIPE_CAP_SHADER_STENCIL_EXPORT: 197 case PIPE_CAP_TGSI_TEXCOORD: 198 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: 199 case PIPE_CAP_TEXTURE_MULTISAMPLE: 200 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 201 case PIPE_CAP_QUERY_MEMORY_INFO: 202 case PIPE_CAP_PCI_GROUP: 203 case PIPE_CAP_PCI_BUS: 204 case PIPE_CAP_PCI_DEVICE: 205 case PIPE_CAP_PCI_FUNCTION: 206 return 0; 207 208 case PIPE_CAP_SM3: 209 case PIPE_CAP_PRIMITIVE_RESTART: 210 case PIPE_CAP_TGSI_INSTANCEID: 211 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 212 case PIPE_CAP_INDEP_BLEND_ENABLE: 213 case PIPE_CAP_INDEP_BLEND_FUNC: 214 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: 215 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: 216 case PIPE_CAP_CONDITIONAL_RENDER: 217 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: 218 case PIPE_CAP_FAKE_SW_MSAA: 219 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 220 case PIPE_CAP_CLIP_HALFZ: 221 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen); 222 223 case PIPE_CAP_DEPTH_CLIP_DISABLE: 224 return is_a3xx(screen) || is_a4xx(screen); 225 226 case PIPE_CAP_POLYGON_OFFSET_CLAMP: 227 return is_a5xx(screen); 228 229 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: 230 return 0; 231 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 232 if (is_a3xx(screen)) return 16; 233 if (is_a4xx(screen)) return 32; 234 if (is_a5xx(screen)) return 32; 235 return 0; 236 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: 237 /* We could possibly emulate more by pretending 2d/rect textures and 238 * splitting high bits of index into 2nd dimension.. 239 */ 240 if (is_a3xx(screen)) return 8192; 241 if (is_a4xx(screen)) return 16384; 242 if (is_a5xx(screen)) return 16384; 243 return 0; 244 245 case PIPE_CAP_TEXTURE_FLOAT_LINEAR: 246 case PIPE_CAP_CUBE_MAP_ARRAY: 247 case PIPE_CAP_SAMPLER_VIEW_TARGET: 248 case PIPE_CAP_TEXTURE_QUERY_LOD: 249 return is_a4xx(screen) || is_a5xx(screen); 250 251 case PIPE_CAP_START_INSTANCE: 252 /* Note that a5xx can do this, it just can't (at least with 253 * current firmware) do draw_indirect with base_instance. 254 * Since draw_indirect is needed sooner (gles31 and gl40 vs 255 * gl42), hide base_instance on a5xx. :-/ 256 */ 257 return is_a4xx(screen); 258 259 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 260 return 64; 261 262 case PIPE_CAP_GLSL_FEATURE_LEVEL: 263 if (glsl120) 264 return 120; 265 return is_ir3(screen) ? 140 : 120; 266 267 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: 268 if (is_a5xx(screen)) 269 return 4; 270 return 0; 271 272 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: 273 if (is_a4xx(screen) || is_a5xx(screen)) 274 return 4; 275 return 0; 276 277 /* Unsupported features. */ 278 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 279 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 280 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 281 case PIPE_CAP_USER_VERTEX_BUFFERS: 282 case PIPE_CAP_QUERY_PIPELINE_STATISTICS: 283 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: 284 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: 285 case PIPE_CAP_TEXTURE_GATHER_SM5: 286 case PIPE_CAP_SAMPLE_SHADING: 287 case PIPE_CAP_TEXTURE_GATHER_OFFSETS: 288 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: 289 case PIPE_CAP_MULTI_DRAW_INDIRECT: 290 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: 291 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: 292 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: 293 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: 294 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: 295 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: 296 case PIPE_CAP_DEPTH_BOUNDS_TEST: 297 case PIPE_CAP_TGSI_TXQS: 298 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */ 299 case PIPE_CAP_FORCE_PERSAMPLE_INTERP: 300 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: 301 case PIPE_CAP_CLEAR_TEXTURE: 302 case PIPE_CAP_DRAW_PARAMETERS: 303 case PIPE_CAP_TGSI_PACK_HALF_FLOAT: 304 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: 305 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: 306 case PIPE_CAP_GENERATE_MIPMAP: 307 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: 308 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: 309 case PIPE_CAP_CULL_DISTANCE: 310 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: 311 case PIPE_CAP_TGSI_VOTE: 312 case PIPE_CAP_MAX_WINDOW_RECTANGLES: 313 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: 314 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: 315 case PIPE_CAP_TGSI_ARRAY_COMPONENTS: 316 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: 317 case PIPE_CAP_TGSI_FS_FBFETCH: 318 case PIPE_CAP_TGSI_MUL_ZERO_WINS: 319 case PIPE_CAP_DOUBLES: 320 case PIPE_CAP_INT64: 321 case PIPE_CAP_INT64_DIVMOD: 322 case PIPE_CAP_TGSI_TEX_TXF_LZ: 323 case PIPE_CAP_TGSI_CLOCK: 324 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: 325 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: 326 case PIPE_CAP_TGSI_BALLOT: 327 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: 328 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: 329 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: 330 case PIPE_CAP_POST_DEPTH_COVERAGE: 331 case PIPE_CAP_BINDLESS_TEXTURE: 332 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: 333 case PIPE_CAP_QUERY_SO_OVERFLOW: 334 case PIPE_CAP_MEMOBJ: 335 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: 336 case PIPE_CAP_TILE_RASTER_ORDER: 337 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: 338 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: 339 return 0; 340 341 case PIPE_CAP_CONTEXT_PRIORITY_MASK: 342 return screen->priority_mask; 343 344 case PIPE_CAP_DRAW_INDIRECT: 345 if (is_a4xx(screen) || is_a5xx(screen)) 346 return 1; 347 return 0; 348 349 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: 350 if (is_a4xx(screen) || is_a5xx(screen)) 351 return 1; 352 return 0; 353 354 case PIPE_CAP_LOAD_CONSTBUF: 355 /* name is confusing, but this turns on std430 packing */ 356 if (is_ir3(screen)) 357 return 1; 358 return 0; 359 360 case PIPE_CAP_MAX_VIEWPORTS: 361 return 1; 362 363 case PIPE_CAP_SHAREABLE_SHADERS: 364 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: 365 /* manage the variants for these ourself, to avoid breaking precompile: */ 366 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 367 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 368 if (is_ir3(screen)) 369 return 1; 370 return 0; 371 372 /* Stream output. */ 373 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 374 if (is_ir3(screen)) 375 return PIPE_MAX_SO_BUFFERS; 376 return 0; 377 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 378 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: 379 if (is_ir3(screen)) 380 return 1; 381 return 0; 382 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 383 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 384 if (is_ir3(screen)) 385 return 16 * 4; /* should only be shader out limit? */ 386 return 0; 387 388 /* Geometry shader output, unsupported. */ 389 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: 390 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: 391 case PIPE_CAP_MAX_VERTEX_STREAMS: 392 return 0; 393 394 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: 395 return 2048; 396 397 /* Texturing. */ 398 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 399 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 400 return MAX_MIP_LEVELS; 401 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 402 return 11; 403 404 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 405 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0; 406 407 /* Render targets. */ 408 case PIPE_CAP_MAX_RENDER_TARGETS: 409 return screen->max_rts; 410 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 411 return is_a3xx(screen) ? 1 : 0; 412 413 /* Queries. */ 414 case PIPE_CAP_QUERY_BUFFER_OBJECT: 415 return 0; 416 case PIPE_CAP_OCCLUSION_QUERY: 417 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen); 418 case PIPE_CAP_QUERY_TIMESTAMP: 419 case PIPE_CAP_QUERY_TIME_ELAPSED: 420 /* only a4xx, requires new enough kernel so we know max_freq: */ 421 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen)); 422 423 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: 424 case PIPE_CAP_MIN_TEXEL_OFFSET: 425 return -8; 426 427 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: 428 case PIPE_CAP_MAX_TEXEL_OFFSET: 429 return 7; 430 431 case PIPE_CAP_ENDIANNESS: 432 return PIPE_ENDIAN_LITTLE; 433 434 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 435 return 64; 436 437 case PIPE_CAP_VENDOR_ID: 438 return 0x5143; 439 case PIPE_CAP_DEVICE_ID: 440 return 0xFFFFFFFF; 441 case PIPE_CAP_ACCELERATED: 442 return 1; 443 case PIPE_CAP_VIDEO_MEMORY: 444 DBG("FINISHME: The value returned is incorrect\n"); 445 return 10; 446 case PIPE_CAP_UMA: 447 return 1; 448 case PIPE_CAP_NATIVE_FENCE_FD: 449 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD; 450 } 451 debug_printf("unknown param %d\n", param); 452 return 0; 453 } 454 455 static float 456 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 457 { 458 switch (param) { 459 case PIPE_CAPF_MAX_LINE_WIDTH: 460 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 461 /* NOTE: actual value is 127.0f, but this is working around a deqp 462 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide 463 * uses too small of a render target size, and gets confused when 464 * the lines start going offscreen. 465 * 466 * See: https://code.google.com/p/android/issues/detail?id=206513 467 */ 468 if (fd_mesa_debug & FD_DBG_DEQP) 469 return 48.0f; 470 return 127.0f; 471 case PIPE_CAPF_MAX_POINT_WIDTH: 472 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 473 return 4092.0f; 474 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 475 return 16.0f; 476 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 477 return 15.0f; 478 case PIPE_CAPF_GUARD_BAND_LEFT: 479 case PIPE_CAPF_GUARD_BAND_TOP: 480 case PIPE_CAPF_GUARD_BAND_RIGHT: 481 case PIPE_CAPF_GUARD_BAND_BOTTOM: 482 return 0.0f; 483 } 484 debug_printf("unknown paramf %d\n", param); 485 return 0; 486 } 487 488 static int 489 fd_screen_get_shader_param(struct pipe_screen *pscreen, 490 enum pipe_shader_type shader, 491 enum pipe_shader_cap param) 492 { 493 struct fd_screen *screen = fd_screen(pscreen); 494 495 switch(shader) 496 { 497 case PIPE_SHADER_FRAGMENT: 498 case PIPE_SHADER_VERTEX: 499 break; 500 case PIPE_SHADER_COMPUTE: 501 if (has_compute(screen)) 502 break; 503 return 0; 504 case PIPE_SHADER_GEOMETRY: 505 /* maye we could emulate.. */ 506 return 0; 507 default: 508 DBG("unknown shader type %d", shader); 509 return 0; 510 } 511 512 /* this is probably not totally correct.. but it's a start: */ 513 switch (param) { 514 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 515 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 516 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 517 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 518 return 16384; 519 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 520 return 8; /* XXX */ 521 case PIPE_SHADER_CAP_MAX_INPUTS: 522 case PIPE_SHADER_CAP_MAX_OUTPUTS: 523 return 16; 524 case PIPE_SHADER_CAP_MAX_TEMPS: 525 return 64; /* Max native temporaries. */ 526 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: 527 /* NOTE: seems to be limit for a3xx is actually 512 but 528 * split between VS and FS. Use lower limit of 256 to 529 * avoid getting into impossible situations: 530 */ 531 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]); 532 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 533 return is_ir3(screen) ? 16 : 1; 534 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 535 return 1; 536 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 537 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 538 /* Technically this should be the same as for TEMP/CONST, since 539 * everything is just normal registers. This is just temporary 540 * hack until load_input/store_output handle arrays in a similar 541 * way as load_var/store_var.. 542 */ 543 return 0; 544 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 545 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 546 /* a2xx compiler doesn't handle indirect: */ 547 return is_ir3(screen) ? 1 : 0; 548 case PIPE_SHADER_CAP_SUBROUTINES: 549 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: 550 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: 551 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: 552 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: 553 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 554 return 0; 555 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 556 return 1; 557 case PIPE_SHADER_CAP_INTEGERS: 558 if (glsl120) 559 return 0; 560 return is_ir3(screen) ? 1 : 0; 561 case PIPE_SHADER_CAP_INT64_ATOMICS: 562 return 0; 563 case PIPE_SHADER_CAP_FP16: 564 return 0; 565 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 566 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 567 return 16; 568 case PIPE_SHADER_CAP_PREFERRED_IR: 569 if (is_ir3(screen)) 570 return PIPE_SHADER_IR_NIR; 571 return PIPE_SHADER_IR_TGSI; 572 case PIPE_SHADER_CAP_SUPPORTED_IRS: 573 if (is_ir3(screen)) { 574 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI); 575 } else { 576 return (1 << PIPE_SHADER_IR_TGSI); 577 } 578 return 0; 579 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: 580 return 32; 581 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: 582 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: 583 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 584 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 585 return 0; 586 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 587 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 588 if (is_a5xx(screen)) { 589 /* a5xx (and a4xx for that matter) has one state-block 590 * for compute-shader SSBO's and another that is shared 591 * by VS/HS/DS/GS/FS.. so to simplify things for now 592 * just advertise SSBOs for FS and CS. We could possibly 593 * do what blob does, and partition the space for 594 * VS/HS/DS/GS/FS. The blob advertises: 595 * 596 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4 597 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4 598 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4 599 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4 600 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4 601 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24 602 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24 603 * 604 * I think that way we could avoid having to patch shaders 605 * for actual SSBO indexes by using a static partitioning. 606 * 607 * Note same state block is used for images and buffers, 608 * but images also need texture state for read access 609 * (isam/isam.3d) 610 */ 611 switch(shader) 612 { 613 case PIPE_SHADER_FRAGMENT: 614 case PIPE_SHADER_COMPUTE: 615 return 24; 616 default: 617 return 0; 618 } 619 } 620 return 0; 621 } 622 debug_printf("unknown shader param %d\n", param); 623 return 0; 624 } 625 626 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this 627 * into per-generation backend? 628 */ 629 static int 630 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type, 631 enum pipe_compute_cap param, void *ret) 632 { 633 struct fd_screen *screen = fd_screen(pscreen); 634 const char * const ir = "ir3"; 635 636 if (!has_compute(screen)) 637 return 0; 638 639 switch (param) { 640 case PIPE_COMPUTE_CAP_ADDRESS_BITS: 641 if (ret) { 642 uint32_t *address_bits = ret; 643 address_bits[0] = 32; 644 645 if (is_a5xx(screen)) 646 address_bits[0] = 64; 647 } 648 return 1 * sizeof(uint32_t); 649 650 case PIPE_COMPUTE_CAP_IR_TARGET: 651 if (ret) 652 sprintf(ret, ir); 653 return strlen(ir) * sizeof(char); 654 655 case PIPE_COMPUTE_CAP_GRID_DIMENSION: 656 if (ret) { 657 uint64_t *grid_dimension = ret; 658 grid_dimension[0] = 3; 659 } 660 return 1 * sizeof(uint64_t); 661 662 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: 663 if (ret) { 664 uint64_t *grid_size = ret; 665 grid_size[0] = 65535; 666 grid_size[1] = 65535; 667 grid_size[2] = 65535; 668 } 669 return 3 * sizeof(uint64_t) ; 670 671 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: 672 if (ret) { 673 uint64_t *block_size = ret; 674 block_size[0] = 1024; 675 block_size[1] = 1024; 676 block_size[2] = 64; 677 } 678 return 3 * sizeof(uint64_t) ; 679 680 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: 681 if (ret) { 682 uint64_t *max_threads_per_block = ret; 683 *max_threads_per_block = 1024; 684 } 685 return sizeof(uint64_t); 686 687 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: 688 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: 689 if (ret) { 690 uint64_t *local_size = ret; 691 *local_size = 32768; 692 } 693 return sizeof(uint64_t); 694 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: 695 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: 696 break; 697 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE: 698 if (ret) { 699 uint64_t *max = ret; 700 *max = 32768; 701 } 702 return sizeof(uint64_t); 703 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY: 704 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: 705 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: 706 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE: 707 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: 708 break; 709 } 710 711 return 0; 712 } 713 714 static const void * 715 fd_get_compiler_options(struct pipe_screen *pscreen, 716 enum pipe_shader_ir ir, unsigned shader) 717 { 718 struct fd_screen *screen = fd_screen(pscreen); 719 720 if (is_ir3(screen)) 721 return ir3_get_compiler_options(screen->compiler); 722 723 return NULL; 724 } 725 726 boolean 727 fd_screen_bo_get_handle(struct pipe_screen *pscreen, 728 struct fd_bo *bo, 729 unsigned stride, 730 struct winsys_handle *whandle) 731 { 732 whandle->stride = stride; 733 734 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { 735 return fd_bo_get_name(bo, &whandle->handle) == 0; 736 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { 737 whandle->handle = fd_bo_handle(bo); 738 return TRUE; 739 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { 740 whandle->handle = fd_bo_dmabuf(bo); 741 return TRUE; 742 } else { 743 return FALSE; 744 } 745 } 746 747 struct fd_bo * 748 fd_screen_bo_from_handle(struct pipe_screen *pscreen, 749 struct winsys_handle *whandle) 750 { 751 struct fd_screen *screen = fd_screen(pscreen); 752 struct fd_bo *bo; 753 754 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { 755 bo = fd_bo_from_name(screen->dev, whandle->handle); 756 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { 757 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0); 758 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { 759 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle); 760 } else { 761 DBG("Attempt to import unsupported handle type %d", whandle->type); 762 return NULL; 763 } 764 765 if (!bo) { 766 DBG("ref name 0x%08x failed", whandle->handle); 767 return NULL; 768 } 769 770 return bo; 771 } 772 773 struct pipe_screen * 774 fd_screen_create(struct fd_device *dev) 775 { 776 struct fd_screen *screen = CALLOC_STRUCT(fd_screen); 777 struct pipe_screen *pscreen; 778 uint64_t val; 779 780 fd_mesa_debug = debug_get_option_fd_mesa_debug(); 781 782 if (fd_mesa_debug & FD_DBG_NOBIN) 783 fd_binning_enabled = false; 784 785 glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120); 786 787 if (!screen) 788 return NULL; 789 790 pscreen = &screen->base; 791 792 screen->dev = dev; 793 screen->refcnt = 1; 794 795 // maybe this should be in context? 796 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D); 797 if (!screen->pipe) { 798 DBG("could not create 3d pipe"); 799 goto fail; 800 } 801 802 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) { 803 DBG("could not get GMEM size"); 804 goto fail; 805 } 806 screen->gmemsize_bytes = val; 807 808 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) { 809 DBG("could not get device-id"); 810 goto fail; 811 } 812 screen->device_id = val; 813 814 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) { 815 DBG("could not get gpu freq"); 816 /* this limits what performance related queries are 817 * supported but is not fatal 818 */ 819 screen->max_freq = 0; 820 } else { 821 screen->max_freq = val; 822 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0) 823 screen->has_timestamp = true; 824 } 825 826 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) { 827 DBG("could not get gpu-id"); 828 goto fail; 829 } 830 screen->gpu_id = val; 831 832 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) { 833 DBG("could not get chip-id"); 834 /* older kernels may not have this property: */ 835 unsigned core = screen->gpu_id / 100; 836 unsigned major = (screen->gpu_id % 100) / 10; 837 unsigned minor = screen->gpu_id % 10; 838 unsigned patch = 0; /* assume the worst */ 839 val = (patch & 0xff) | ((minor & 0xff) << 8) | 840 ((major & 0xff) << 16) | ((core & 0xff) << 24); 841 } 842 screen->chip_id = val; 843 844 if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) { 845 DBG("could not get # of rings"); 846 screen->priority_mask = 0; 847 } else { 848 /* # of rings equates to number of unique priority values: */ 849 screen->priority_mask = (1 << val) - 1; 850 } 851 852 DBG("Pipe Info:"); 853 DBG(" GPU-id: %d", screen->gpu_id); 854 DBG(" Chip-id: 0x%08x", screen->chip_id); 855 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes); 856 857 /* explicitly checking for GPU revisions that are known to work. This 858 * may be overly conservative for a3xx, where spoofing the gpu_id with 859 * the blob driver seems to generate identical cmdstream dumps. But 860 * on a2xx, there seem to be small differences between the GPU revs 861 * so it is probably better to actually test first on real hardware 862 * before enabling: 863 * 864 * If you have a different adreno version, feel free to add it to one 865 * of the cases below and see what happens. And if it works, please 866 * send a patch ;-) 867 */ 868 switch (screen->gpu_id) { 869 case 220: 870 fd2_screen_init(pscreen); 871 break; 872 case 305: 873 case 307: 874 case 320: 875 case 330: 876 fd3_screen_init(pscreen); 877 break; 878 case 420: 879 case 430: 880 fd4_screen_init(pscreen); 881 break; 882 case 530: 883 fd5_screen_init(pscreen); 884 break; 885 default: 886 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id); 887 goto fail; 888 } 889 890 if (screen->gpu_id >= 500) { 891 screen->gmem_alignw = 64; 892 screen->gmem_alignh = 32; 893 screen->num_vsc_pipes = 16; 894 } else { 895 screen->gmem_alignw = 32; 896 screen->gmem_alignh = 32; 897 screen->num_vsc_pipes = 8; 898 } 899 900 /* NOTE: don't enable reordering on a2xx, since completely untested. 901 * Also, don't enable if we have too old of a kernel to support 902 * growable cmdstream buffers, since memory requirement for cmdstream 903 * buffers would be too much otherwise. 904 */ 905 if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)) 906 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER); 907 908 fd_bc_init(&screen->batch_cache); 909 910 (void) mtx_init(&screen->lock, mtx_plain); 911 912 pscreen->destroy = fd_screen_destroy; 913 pscreen->get_param = fd_screen_get_param; 914 pscreen->get_paramf = fd_screen_get_paramf; 915 pscreen->get_shader_param = fd_screen_get_shader_param; 916 pscreen->get_compute_param = fd_get_compute_param; 917 pscreen->get_compiler_options = fd_get_compiler_options; 918 919 fd_resource_screen_init(pscreen); 920 fd_query_screen_init(pscreen); 921 922 pscreen->get_name = fd_screen_get_name; 923 pscreen->get_vendor = fd_screen_get_vendor; 924 pscreen->get_device_vendor = fd_screen_get_device_vendor; 925 926 pscreen->get_timestamp = fd_screen_get_timestamp; 927 928 pscreen->fence_reference = fd_fence_ref; 929 pscreen->fence_finish = fd_fence_finish; 930 pscreen->fence_get_fd = fd_fence_get_fd; 931 932 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16); 933 934 return pscreen; 935 936 fail: 937 fd_screen_destroy(pscreen); 938 return NULL; 939 } 940
