1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __FSL_EPU_H 7 #define __FSL_EPU_H 8 9 #include <asm/types.h> 10 11 #define FSL_STRIDE_4B 4 12 #define FSL_STRIDE_8B 8 13 14 /* Block offsets */ 15 #define EPU_BLOCK_OFFSET 0x00000000 16 17 /* EPGCR (Event Processor Global Control Register) */ 18 #define EPGCR 0x000 19 20 /* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */ 21 #define EPEVTCR0 0x050 22 #define EPEVTCR9 0x074 23 #define EPEVTCR_STRIDE FSL_STRIDE_4B 24 25 /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */ 26 #define EPXTRIGCR 0x090 27 28 /* EPIMCR0-31 (Event Processor Input Mux Control Registers) */ 29 #define EPIMCR0 0x100 30 #define EPIMCR31 0x17C 31 #define EPIMCR_STRIDE FSL_STRIDE_4B 32 33 /* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */ 34 #define EPSMCR0 0x200 35 #define EPSMCR15 0x278 36 #define EPSMCR_STRIDE FSL_STRIDE_8B 37 38 /* EPECR0-15 (Event Processor Event Control Registers) */ 39 #define EPECR0 0x300 40 #define EPECR15 0x33C 41 #define EPECR_STRIDE FSL_STRIDE_4B 42 43 /* EPACR0-15 (Event Processor Action Control Registers) */ 44 #define EPACR0 0x400 45 #define EPACR15 0x43C 46 #define EPACR_STRIDE FSL_STRIDE_4B 47 48 /* EPCCRi0-15 (Event Processor Counter Control Registers) */ 49 #define EPCCR0 0x800 50 #define EPCCR15 0x83C 51 #define EPCCR31 0x87C 52 #define EPCCR_STRIDE FSL_STRIDE_4B 53 54 /* EPCMPR0-15 (Event Processor Counter Compare Registers) */ 55 #define EPCMPR0 0x900 56 #define EPCMPR15 0x93C 57 #define EPCMPR31 0x97C 58 #define EPCMPR_STRIDE FSL_STRIDE_4B 59 60 /* EPCTR0-31 (Event Processor Counter Register) */ 61 #define EPCTR0 0xA00 62 #define EPCTR31 0xA7C 63 #define EPCTR_STRIDE FSL_STRIDE_4B 64 65 #define FSM_END_FLAG 0xFFFFFFFFUL 66 67 struct fsm_reg_vals { 68 u32 offset; 69 u32 value; 70 }; 71 72 void fsl_epu_setup(void *epu_base); 73 void fsl_epu_clean(void *epu_base); 74 75 #endif 76
