1 /* 2 * Copyright (c) 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "common/gen_l3_config.h" 25 26 #include "brw_context.h" 27 #include "brw_defines.h" 28 #include "brw_state.h" 29 #include "intel_batchbuffer.h" 30 31 /** 32 * Calculate the desired L3 partitioning based on the current state of the 33 * pipeline. For now this simply returns the conservative defaults calculated 34 * by get_default_l3_weights(), but we could probably do better by gathering 35 * more statistics from the pipeline state (e.g. guess of expected URB usage 36 * and bound surfaces), or by using feed-back from performance counters. 37 */ 38 static struct gen_l3_weights 39 get_pipeline_state_l3_weights(const struct brw_context *brw) 40 { 41 const struct brw_stage_state *stage_states[] = { 42 [MESA_SHADER_VERTEX] = &brw->vs.base, 43 [MESA_SHADER_TESS_CTRL] = &brw->tcs.base, 44 [MESA_SHADER_TESS_EVAL] = &brw->tes.base, 45 [MESA_SHADER_GEOMETRY] = &brw->gs.base, 46 [MESA_SHADER_FRAGMENT] = &brw->wm.base, 47 [MESA_SHADER_COMPUTE] = &brw->cs.base 48 }; 49 bool needs_dc = false, needs_slm = false; 50 51 for (unsigned i = 0; i < ARRAY_SIZE(stage_states); i++) { 52 const struct gl_program *prog = 53 brw->ctx._Shader->CurrentProgram[stage_states[i]->stage]; 54 const struct brw_stage_prog_data *prog_data = stage_states[i]->prog_data; 55 56 needs_dc |= (prog && (prog->sh.data->NumAtomicBuffers || 57 prog->sh.data->NumShaderStorageBlocks || 58 prog->info.num_images)) || 59 (prog_data && prog_data->total_scratch); 60 needs_slm |= prog_data && prog_data->total_shared; 61 } 62 63 return gen_get_default_l3_weights(&brw->screen->devinfo, 64 needs_dc, needs_slm); 65 } 66 67 /** 68 * Program the hardware to use the specified L3 configuration. 69 */ 70 static void 71 setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg) 72 { 73 const struct gen_device_info *devinfo = &brw->screen->devinfo; 74 const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL]; 75 const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] || 76 cfg->n[GEN_L3P_ALL]; 77 const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] || 78 cfg->n[GEN_L3P_ALL]; 79 const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] || 80 cfg->n[GEN_L3P_ALL]; 81 const bool has_slm = cfg->n[GEN_L3P_SLM]; 82 83 /* According to the hardware docs, the L3 partitioning can only be changed 84 * while the pipeline is completely drained and the caches are flushed, 85 * which involves a first PIPE_CONTROL flush which stalls the pipeline... 86 */ 87 brw_emit_pipe_control_flush(brw, 88 PIPE_CONTROL_DATA_CACHE_FLUSH | 89 PIPE_CONTROL_NO_WRITE | 90 PIPE_CONTROL_CS_STALL); 91 92 /* ...followed by a second pipelined PIPE_CONTROL that initiates 93 * invalidation of the relevant caches. Note that because RO invalidation 94 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL 95 * command is processed by the CS) we cannot combine it with the previous 96 * stalling flush as the hardware documentation suggests, because that 97 * would cause the CS to stall on previous rendering *after* RO 98 * invalidation and wouldn't prevent the RO caches from being polluted by 99 * concurrent rendering before the stall completes. This intentionally 100 * doesn't implement the SKL+ hardware workaround suggesting to enable CS 101 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for 102 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs 103 * already guarantee that there is no concurrent GPGPU kernel execution 104 * (see SKL HSD 2132585). 105 */ 106 brw_emit_pipe_control_flush(brw, 107 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | 108 PIPE_CONTROL_CONST_CACHE_INVALIDATE | 109 PIPE_CONTROL_INSTRUCTION_INVALIDATE | 110 PIPE_CONTROL_STATE_CACHE_INVALIDATE | 111 PIPE_CONTROL_NO_WRITE); 112 113 /* Now send a third stalling flush to make sure that invalidation is 114 * complete when the L3 configuration registers are modified. 115 */ 116 brw_emit_pipe_control_flush(brw, 117 PIPE_CONTROL_DATA_CACHE_FLUSH | 118 PIPE_CONTROL_NO_WRITE | 119 PIPE_CONTROL_CS_STALL); 120 121 if (devinfo->gen >= 8) { 122 assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]); 123 124 const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) | 125 SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) | 126 SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) | 127 SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) | 128 SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC)); 129 130 /* Set up the L3 partitioning. */ 131 brw_load_register_imm32(brw, GEN8_L3CNTLREG, imm_data); 132 } else { 133 assert(!cfg->n[GEN_L3P_ALL]); 134 135 /* When enabled SLM only uses a portion of the L3 on half of the banks, 136 * the matching space on the remaining banks has to be allocated to a 137 * client (URB for all validated configurations) set to the 138 * lower-bandwidth 2-bank address hashing mode. 139 */ 140 const bool urb_low_bw = has_slm && !devinfo->is_baytrail; 141 assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]); 142 143 /* Minimum number of ways that can be allocated to the URB. */ 144 const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0); 145 assert(cfg->n[GEN_L3P_URB] >= n0_urb); 146 147 BEGIN_BATCH(7); 148 OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2)); 149 150 /* Demote any clients with no ways assigned to LLC. */ 151 OUT_BATCH(GEN7_L3SQCREG1); 152 OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT : 153 devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT : 154 IVB_L3SQCREG1_SQGHPCI_DEFAULT) | 155 (has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) | 156 (has_is ? 0 : GEN7_L3SQCREG1_CONV_IS_UC) | 157 (has_c ? 0 : GEN7_L3SQCREG1_CONV_C_UC) | 158 (has_t ? 0 : GEN7_L3SQCREG1_CONV_T_UC)); 159 160 /* Set up the L3 partitioning. */ 161 OUT_BATCH(GEN7_L3CNTLREG2); 162 OUT_BATCH((has_slm ? GEN7_L3CNTLREG2_SLM_ENABLE : 0) | 163 SET_FIELD(cfg->n[GEN_L3P_URB] - n0_urb, GEN7_L3CNTLREG2_URB_ALLOC) | 164 (urb_low_bw ? GEN7_L3CNTLREG2_URB_LOW_BW : 0) | 165 SET_FIELD(cfg->n[GEN_L3P_ALL], GEN7_L3CNTLREG2_ALL_ALLOC) | 166 SET_FIELD(cfg->n[GEN_L3P_RO], GEN7_L3CNTLREG2_RO_ALLOC) | 167 SET_FIELD(cfg->n[GEN_L3P_DC], GEN7_L3CNTLREG2_DC_ALLOC)); 168 OUT_BATCH(GEN7_L3CNTLREG3); 169 OUT_BATCH(SET_FIELD(cfg->n[GEN_L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) | 170 SET_FIELD(cfg->n[GEN_L3P_C], GEN7_L3CNTLREG3_C_ALLOC) | 171 SET_FIELD(cfg->n[GEN_L3P_T], GEN7_L3CNTLREG3_T_ALLOC)); 172 173 ADVANCE_BATCH(); 174 175 if (can_do_hsw_l3_atomics(brw->screen)) { 176 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep 177 * them disabled to avoid crashing the system hard. 178 */ 179 BEGIN_BATCH(5); 180 OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2)); 181 OUT_BATCH(HSW_SCRATCH1); 182 OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE); 183 OUT_BATCH(HSW_ROW_CHICKEN3); 184 OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE) | 185 (has_dc ? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE)); 186 ADVANCE_BATCH(); 187 } 188 } 189 } 190 191 /** 192 * Update the URB size in the context state for the specified L3 193 * configuration. 194 */ 195 static void 196 update_urb_size(struct brw_context *brw, const struct gen_l3_config *cfg) 197 { 198 const struct gen_device_info *devinfo = &brw->screen->devinfo; 199 const unsigned sz = gen_get_l3_config_urb_size(devinfo, cfg); 200 201 if (brw->urb.size != sz) { 202 brw->urb.size = sz; 203 brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE; 204 205 /* If we change the total URB size, reset the individual stage sizes to 206 * zero so that, even if there is no URB size change, gen7_upload_urb 207 * still re-emits 3DSTATE_URB_*. 208 */ 209 brw->urb.vsize = 0; 210 brw->urb.gsize = 0; 211 brw->urb.hsize = 0; 212 brw->urb.dsize = 0; 213 } 214 } 215 216 static void 217 emit_l3_state(struct brw_context *brw) 218 { 219 const struct gen_l3_weights w = get_pipeline_state_l3_weights(brw); 220 const float dw = gen_diff_l3_weights(w, gen_get_l3_config_weights(brw->l3.config)); 221 /* The distance between any two compatible weight vectors cannot exceed two 222 * due to the triangle inequality. 223 */ 224 const float large_dw_threshold = 2.0; 225 /* Somewhat arbitrary, simply makes sure that there will be no repeated 226 * transitions to the same L3 configuration, could probably do better here. 227 */ 228 const float small_dw_threshold = 0.5; 229 /* If we're emitting a new batch the caches should already be clean and the 230 * transition should be relatively cheap, so it shouldn't hurt much to use 231 * the smaller threshold. Otherwise use the larger threshold so that we 232 * only reprogram the L3 mid-batch if the most recently programmed 233 * configuration is incompatible with the current pipeline state. 234 */ 235 const float dw_threshold = (brw->ctx.NewDriverState & BRW_NEW_BATCH ? 236 small_dw_threshold : large_dw_threshold); 237 238 if (dw > dw_threshold && can_do_pipelined_register_writes(brw->screen)) { 239 const struct gen_l3_config *const cfg = 240 gen_get_l3_config(&brw->screen->devinfo, w); 241 242 setup_l3_config(brw, cfg); 243 update_urb_size(brw, cfg); 244 brw->l3.config = cfg; 245 246 if (unlikely(INTEL_DEBUG & DEBUG_L3)) { 247 fprintf(stderr, "L3 config transition (%f > %f): ", dw, dw_threshold); 248 gen_dump_l3_config(cfg, stderr); 249 } 250 } 251 } 252 253 const struct brw_tracked_state gen7_l3_state = { 254 .dirty = { 255 .mesa = 0, 256 .brw = BRW_NEW_BATCH | 257 BRW_NEW_BLORP | 258 BRW_NEW_CS_PROG_DATA | 259 BRW_NEW_FS_PROG_DATA | 260 BRW_NEW_GS_PROG_DATA | 261 BRW_NEW_TCS_PROG_DATA | 262 BRW_NEW_TES_PROG_DATA | 263 BRW_NEW_VS_PROG_DATA, 264 }, 265 .emit = emit_l3_state 266 }; 267 268 /** 269 * Hack to restore the default L3 configuration. 270 * 271 * This will be called at the end of every batch in order to reset the L3 272 * configuration to the default values for the time being until the kernel is 273 * fixed. Until kernel commit 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b 274 * (included in v4.1) we would set the MI_RESTORE_INHIBIT bit when submitting 275 * batch buffers for the default context used by the DDX, which meant that any 276 * context state changed by the GL would leak into the DDX, the assumption 277 * being that the DDX would initialize any state it cares about manually. The 278 * DDX is however not careful enough to program an L3 configuration 279 * explicitly, and it makes assumptions about it (URB size) which won't hold 280 * and cause it to misrender if we let our L3 set-up to leak into the DDX. 281 * 282 * Since v4.1 of the Linux kernel the default context is saved and restored 283 * normally, so it's far less likely for our L3 programming to interfere with 284 * other contexts -- In fact restoring the default L3 configuration at the end 285 * of the batch will be redundant most of the time. A kind of state leak is 286 * still possible though if the context making assumptions about L3 state is 287 * created immediately after our context was active (e.g. without the DDX 288 * default context being scheduled in between) because at present the DRM 289 * doesn't fully initialize the contents of newly created contexts and instead 290 * sets the MI_RESTORE_INHIBIT flag causing it to inherit the state from the 291 * last active context. 292 * 293 * It's possible to realize such a scenario if, say, an X server (or a GL 294 * application using an outdated non-L3-aware Mesa version) is started while 295 * another GL application is running and happens to have modified the L3 296 * configuration, or if no X server is running at all and a GL application 297 * using a non-L3-aware Mesa version is started after another GL application 298 * ran and modified the L3 configuration -- The latter situation can actually 299 * be reproduced easily on IVB in our CI system. 300 */ 301 void 302 gen7_restore_default_l3_config(struct brw_context *brw) 303 { 304 const struct gen_device_info *devinfo = &brw->screen->devinfo; 305 const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo); 306 307 if (cfg != brw->l3.config && 308 can_do_pipelined_register_writes(brw->screen)) { 309 setup_l3_config(brw, cfg); 310 update_urb_size(brw, cfg); 311 brw->l3.config = cfg; 312 } 313 } 314
