1 /******************************************************************************* 2 * Copyright 1999-2018 Intel Corporation 3 * All Rights Reserved. 4 * 5 * If this software was obtained under the Intel Simplified Software License, 6 * the following terms apply: 7 * 8 * The source code, information and material ("Material") contained herein is 9 * owned by Intel Corporation or its suppliers or licensors, and title to such 10 * Material remains with Intel Corporation or its suppliers or licensors. The 11 * Material contains proprietary information of Intel or its suppliers and 12 * licensors. The Material is protected by worldwide copyright laws and treaty 13 * provisions. No part of the Material may be used, copied, reproduced, 14 * modified, published, uploaded, posted, transmitted, distributed or disclosed 15 * in any way without Intel's prior express written permission. No license under 16 * any patent, copyright or other intellectual property rights in the Material 17 * is granted to or conferred upon you, either expressly, by implication, 18 * inducement, estoppel or otherwise. Any license under such intellectual 19 * property rights must be express and approved by Intel in writing. 20 * 21 * Unless otherwise agreed by Intel in writing, you may not remove or alter this 22 * notice or any other notice embedded in Materials by Intel or Intel's 23 * suppliers or licensors in any way. 24 * 25 * 26 * If this software was obtained under the Apache License, Version 2.0 (the 27 * "License"), the following terms apply: 28 * 29 * You may not use this file except in compliance with the License. You may 30 * obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 31 * 32 * 33 * Unless required by applicable law or agreed to in writing, software 34 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 35 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 36 * 37 * See the License for the specific language governing permissions and 38 * limitations under the License. 39 *******************************************************************************/ 40 /******* FILE MODIFIED FROM ORIGINAL 2019u1 RELEASE TO AVOID WARNINGS *********/ 41 // 42 // Intel(R) Integrated Performance Primitives (Intel(R) IPP) Cryptography 43 // 44 // Purpose: 45 // Internal definitions 46 // 47 // 48 49 #ifndef __OWNDEFS_H__ 50 #define __OWNDEFS_H__ 51 52 #if defined( _VXWORKS ) 53 #include <vxWorks.h> 54 #undef NONE 55 #endif 56 57 #ifndef IPPCPDEFS_H__ 58 #include "ippcpdefs.h" 59 #endif 60 61 #if defined(__INTEL_COMPILER) || defined(_MSC_VER) 62 #define __INLINE static __inline 63 #elif defined( __GNUC__ ) 64 #define __INLINE static __inline__ 65 #else 66 #define __INLINE static 67 #endif 68 69 #if defined(__INTEL_COMPILER) 70 #define __RESTRICT restrict 71 #elif !defined( __RESTRICT ) 72 #define __RESTRICT 73 #endif 74 75 #if defined( IPP_W32DLL ) 76 #if defined( _MSC_VER ) || defined( __INTEL_COMPILER ) 77 #define IPPDEF(type) __declspec(dllexport) type 78 #else 79 #define IPPDEF(type) type 80 #endif 81 #else 82 #define IPPDEF(type) type 83 #endif 84 85 /* structure represeting 128 bit unsigned integer type */ 86 87 typedef struct{ 88 Ipp64u low; 89 Ipp64u high; 90 }Ipp128u; 91 92 /* ia32 */ 93 #define _IPP_PX 0 /* pure C-code */ 94 #define _IPP_M5 1 /* Intel(R) Quark(TM) processor */ 95 #define _IPP_W7 8 /* Intel(R) Streaming SIMD Extensions 2 (Intel(R) SSE2) */ 96 #define _IPP_T7 16 /* Intel(R) Streaming SIMD Extensions 3 (Intel(R) SSE3) */ 97 #define _IPP_V8 32 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) */ 98 #define _IPP_S8 33 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) + MOVBE instruction */ 99 #define _IPP_P8 64 /* Intel(R) Streaming SIMD Extensions 4.2 (Intel(R) SSE4.2) */ 100 #define _IPP_G9 128 /* Intel(R) Advanced Vector Extensions (Intel(R) AVX) */ 101 #define _IPP_H9 256 /* Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2) */ 102 #define _IPP_I0 512 /* Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX512) - Intel(R) Xeon Phi(TM) Processor (formerly Knights Landing) */ 103 #define _IPP_S0 1024 /* Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX512) - Intel(R) Xeon(R) Processor (formerly codenamed Skylake) */ 104 105 /* intel64 */ 106 #define _IPP32E_PX _IPP_PX /* pure C-code */ 107 #define _IPP32E_M7 32 /* Intel(R) Streaming SIMD Extensions 3 (Intel(R) SSE3) */ 108 #define _IPP32E_U8 64 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) */ 109 #define _IPP32E_N8 65 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) + MOVBE instruction */ 110 #define _IPP32E_Y8 128 /* Intel(R) Streaming SIMD Extensions 4.2 (Intel(R) SSE4.2) */ 111 #define _IPP32E_E9 256 /* Intel(R) Advanced Vector Extensions (Intel(R) AVX) */ 112 #define _IPP32E_L9 512 /* Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2) */ 113 #define _IPP32E_N0 1024 /* Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX512) - Intel(R) Xeon Phi(TM) Processor (formerly Knights Landing) */ 114 #define _IPP32E_K0 2048 /* Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX512) - Intel(R) Xeon(R) Processor (formerly codenamed Skylake) */ 115 116 117 #if defined(__INTEL_COMPILER) || (_MSC_VER >= 1300) 118 #define __ALIGN8 __declspec (align(8)) 119 #define __ALIGN16 __declspec (align(16)) 120 #define __ALIGN32 __declspec (align(32)) 121 #define __ALIGN64 __declspec (align(64)) 122 #elif defined(__GNUC__) 123 #define __ALIGN8 __attribute__((aligned(8))) 124 #define __ALIGN16 __attribute__((aligned(16))) 125 #define __ALIGN32 __attribute__((aligned(32))) 126 #define __ALIGN64 __attribute__((aligned(64))) 127 #else 128 #error Intel, MS or GNU C compiler required 129 #endif 130 131 /* ia32 */ 132 #if defined ( _M5 ) /* Intel(R) Quark(TM) processor */ 133 #define _IPP _IPP_M5 134 #define _IPP32E _IPP32E_PX 135 #define OWNAPI(name) m5_##name 136 137 #elif defined( _W7 ) /* Intel(R) SSE2 */ 138 #define _IPP _IPP_W7 139 #define _IPP32E _IPP32E_PX 140 #define OWNAPI(name) w7_##name 141 142 #elif defined( _T7 ) /* Intel(R) SSE3 */ 143 #define _IPP _IPP_T7 144 #define _IPP32E _IPP32E_PX 145 #define OWNAPI(name) t7_##name 146 147 #elif defined( _V8 ) /* SSSE3 */ 148 #define _IPP _IPP_V8 149 #define _IPP32E _IPP32E_PX 150 #define OWNAPI(name) v8_##name 151 152 #elif defined( _S8 ) /* SSSE3 + MOVBE instruction */ 153 #define _IPP _IPP_S8 154 #define _IPP32E _IPP32E_PX 155 #define OWNAPI(name) s8_##name 156 157 #elif defined( _P8 ) /* Intel(R) SSE4.2 */ 158 #define _IPP _IPP_P8 159 #define _IPP32E _IPP32E_PX 160 #define OWNAPI(name) p8_##name 161 162 #elif defined( _G9 ) /* Intel(R) AVX */ 163 #define _IPP _IPP_G9 164 #define _IPP32E _IPP32E_PX 165 #define OWNAPI(name) g9_##name 166 167 #elif defined( _H9 ) /* Intel(R) AVX2 */ 168 #define _IPP _IPP_H9 169 #define _IPP32E _IPP32E_PX 170 #define OWNAPI(name) h9_##name 171 172 /* intel64 */ 173 #elif defined( _M7 ) /* Intel(R) SSE3 */ 174 #define _IPP _IPP_PX 175 #define _IPP32E _IPP32E_M7 176 #define OWNAPI(name) m7_##name 177 178 #elif defined( _U8 ) /* SSSE3 */ 179 #define _IPP _IPP_PX 180 #define _IPP32E _IPP32E_U8 181 #define OWNAPI(name) u8_##name 182 183 #elif defined( _N8 ) /* SSSE3 + MOVBE instruction */ 184 #define _IPP _IPP_PX 185 #define _IPP32E _IPP32E_N8 186 #define OWNAPI(name) n8_##name 187 188 #elif defined( _Y8 ) /* Intel(R) SSE4.2 */ 189 #define _IPP _IPP_PX 190 #define _IPP32E _IPP32E_Y8 191 #define OWNAPI(name) y8_##name 192 193 #elif defined( _E9 ) /* Intel(R) AVX */ 194 #define _IPP _IPP_PX 195 #define _IPP32E _IPP32E_E9 196 #define OWNAPI(name) e9_##name 197 198 #elif defined( _L9 ) /* Intel(R) AVX2 */ 199 #define _IPP _IPP_PX 200 #define _IPP32E _IPP32E_L9 201 #define OWNAPI(name) l9_##name 202 203 #elif defined( _N0 ) /* Intel(R) AVX512 - formerly Knights Landing */ 204 #define _IPP _IPP_PX 205 #define _IPP32E _IPP32E_N0 206 #define OWNAPI(name) n0_##name 207 208 #elif defined( _K0 ) /* Intel(R) AVX512 - formerly codenamed Skylake */ 209 #define _IPP _IPP_PX 210 #define _IPP32E _IPP32E_K0 211 #define OWNAPI(name) k0_##name 212 213 #else 214 #define _IPP _IPP_PX 215 #define _IPP32E _IPP32E_PX 216 #if defined (_M_AMD64) || defined (__x86_64__) || defined ( _ARCH_EM64T ) 217 #define OWNAPI(name) mx_##name 218 #else 219 #define OWNAPI(name) px_##name 220 #endif 221 #endif 222 223 #ifndef _OWN_MERGED_BLD 224 #undef OWNAPI 225 #define OWNAPI(name) name 226 #endif 227 228 #if defined( IPP_W32DLL ) 229 #if defined( _MSC_VER ) || defined( __INTEL_COMPILER ) 230 #define IPPFUN(type,name,arg) __declspec(dllexport) type IPP_STDCALL name arg 231 #else 232 #define IPPFUN(type,name,arg) extern type IPP_STDCALL name arg 233 #endif 234 #else 235 #define IPPFUN(type,name,arg) extern type IPP_STDCALL name arg 236 #endif 237 238 #define _IPP_ARCH_IA32 1 239 #define _IPP_ARCH_EM64T 4 240 241 #if defined ( _ARCH_IA32 ) 242 #define _IPP_ARCH _IPP_ARCH_IA32 243 244 #elif defined( _ARCH_EM64T ) 245 #define _IPP_ARCH _IPP_ARCH_EM64T 246 247 #else 248 #if defined(_M_AMD64) || defined(__x86_64) || defined(__x86_64__) 249 #define _IPP_ARCH _IPP_ARCH_EM64T 250 251 #else 252 #define _IPP_ARCH _IPP_ARCH_IA32 253 254 #endif 255 #endif 256 257 #if ((_IPP_ARCH == _IPP_ARCH_IA32)) 258 __INLINE 259 Ipp32s IPP_INT_PTR( const void* ptr ) { 260 union { 261 void* Ptr; 262 Ipp32s Int; 263 } dd; 264 dd.Ptr = (void*)ptr; 265 return dd.Int; 266 } 267 268 __INLINE 269 Ipp32u IPP_UINT_PTR( const void* ptr ) { 270 union { 271 void* Ptr; 272 Ipp32u Int; 273 } dd; 274 dd.Ptr = (void*)ptr; 275 return dd.Int; 276 } 277 #elif ((_IPP_ARCH == _IPP_ARCH_EM64T) || (_IPP_ARCH == _IPP_ARCH_LRB2)) 278 __INLINE 279 Ipp64s IPP_INT_PTR( const void* ptr ) { 280 union { 281 void* Ptr; 282 Ipp64s Int; 283 } dd; 284 dd.Ptr = (void*)ptr; 285 return dd.Int; 286 } 287 288 __INLINE 289 Ipp64u IPP_UINT_PTR( const void* ptr ) { 290 union { 291 void* Ptr; 292 Ipp64u Int; 293 } dd; 294 dd.Ptr = (void*)ptr; 295 return dd.Int; 296 } 297 #else 298 #define IPP_INT_PTR( ptr ) ( (long)(ptr) ) 299 #define IPP_UINT_PTR( ptr ) ( (unsigned long)(ptr) ) 300 #endif 301 302 #define IPP_ALIGN_TYPE(type, align) ((align)/sizeof(type)-1) 303 #define IPP_BYTES_TO_ALIGN(ptr, align) ((-(IPP_INT_PTR(ptr)&((align)-1)))&((align)-1)) 304 #define IPP_ALIGNED_PTR(ptr, align) (void*)( (unsigned char*)(ptr) + (IPP_BYTES_TO_ALIGN( ptr, align )) ) 305 306 #define IPP_ALIGNED_SIZE(size, align) (((size)+(align)-1)&~((align)-1)) 307 308 #define IPP_MALLOC_ALIGNED_BYTES 64 309 #define IPP_MALLOC_ALIGNED_8BYTES 8 310 #define IPP_MALLOC_ALIGNED_16BYTES 16 311 #define IPP_MALLOC_ALIGNED_32BYTES 32 312 313 #define IPP_ALIGNED_ARRAY(align,arrtype,arrname,arrlength)\ 314 char arrname##AlignedArrBuff[sizeof(arrtype)*(arrlength)+IPP_ALIGN_TYPE(char, align)];\ 315 arrtype *arrname = (arrtype*)IPP_ALIGNED_PTR(arrname##AlignedArrBuff,align) 316 317 #if defined( __cplusplus ) 318 extern "C" { 319 #endif 320 321 /* ///////////////////////////////////////////////////////////////////////////// 322 323 Intel(R) IPP Context Identification 324 325 /////////////////////////////////////////////////////////////////////////// */ 326 327 #define IPP_CONTEXT( a, b, c, d) \ 328 (int)(((unsigned)(a) << 24) | ((unsigned)(b) << 16) | \ 329 ((unsigned)(c) << 8) | (unsigned)(d)) 330 331 typedef enum { 332 idCtxUnknown = 0, 333 idCtxDES = IPP_CONTEXT( ' ', 'D', 'E', 'S'), 334 idCtxRijndael = IPP_CONTEXT( ' ', 'R', 'I', 'J'), 335 idCtxSMS4 = IPP_CONTEXT( 'S', 'M', 'S', '4'), 336 idCtxARCFOUR = IPP_CONTEXT( ' ', 'R', 'C', '4'), 337 idCtxSHA1 = IPP_CONTEXT( 'S', 'H', 'S', '1'), 338 idCtxSHA224 = IPP_CONTEXT( 'S', 'H', 'S', '3'), 339 idCtxSHA256 = IPP_CONTEXT( 'S', 'H', 'S', '2'), 340 idCtxSHA384 = IPP_CONTEXT( 'S', 'H', 'S', '4'), 341 idCtxSHA512 = IPP_CONTEXT( 'S', 'H', 'S', '5'), 342 idCtxMD5 = IPP_CONTEXT( ' ', 'M', 'D', '5'), 343 idCtxHMAC = IPP_CONTEXT( 'H', 'M', 'A', 'C'), 344 idCtxBigNum = IPP_CONTEXT( 'B', 'I', 'G', 'N'), 345 idCtxMontgomery = IPP_CONTEXT( 'M', 'O', 'N', 'T'), 346 idCtxPrimeNumber = IPP_CONTEXT( 'P', 'R', 'I', 'M'), 347 idCtxPRNG = IPP_CONTEXT( 'P', 'R', 'N', 'G'), 348 idCtxRSA = IPP_CONTEXT( ' ', 'R', 'S', 'A'), 349 idCtxRSA_PubKey = IPP_CONTEXT( 'R', 'S', 'A', '0'), 350 idCtxRSA_PrvKey1 = IPP_CONTEXT( 'R', 'S', 'A', '1'), 351 idCtxRSA_PrvKey2 = IPP_CONTEXT( 'R', 'S', 'A', '2'), 352 idCtxDSA = IPP_CONTEXT( ' ', 'D', 'S', 'A'), 353 idCtxECCP = IPP_CONTEXT( ' ', 'E', 'C', 'P'), 354 idCtxECCB = IPP_CONTEXT( ' ', 'E', 'C', 'B'), 355 idCtxECCPPoint = IPP_CONTEXT( 'P', 'E', 'C', 'P'), 356 idCtxECCBPoint = IPP_CONTEXT( 'P', 'E', 'C', 'B'), 357 idCtxDH = IPP_CONTEXT( ' ', ' ', 'D', 'H'), 358 idCtxDLP = IPP_CONTEXT( ' ', 'D', 'L', 'P'), 359 idCtxCMAC = IPP_CONTEXT( 'C', 'M', 'A', 'C'), 360 idCtxAESXCBC, 361 idCtxAESCCM, 362 idCtxAESGCM, 363 idCtxGFP, 364 idCtxGFPE, 365 idCtxGFPX, 366 idCtxGFPXE, 367 idCtxGFPXQX, 368 idCtxGFPXQXE, 369 idCtxGFPEC, 370 idCtxGFPPoint, 371 idCtxGFPXEC, 372 idCtxGFPXECPoint, 373 idCtxHash, 374 idCtxSM3, 375 idCtxAESXTS, 376 idxCtxECES_SM2 377 } IppCtxId; 378 379 380 381 382 /* ///////////////////////////////////////////////////////////////////////////// 383 Helpers 384 /////////////////////////////////////////////////////////////////////////// */ 385 386 #define IPP_NOERROR_RET() return ippStsNoErr 387 #define IPP_ERROR_RET( ErrCode ) return (ErrCode) 388 389 #ifdef _IPP_DEBUG 390 391 #define IPP_BADARG_RET( expr, ErrCode )\ 392 {if (expr) { IPP_ERROR_RET( ErrCode ); }} 393 394 #else 395 396 #define IPP_BADARG_RET( expr, ErrCode ) 397 398 #endif 399 400 401 #define IPP_BAD_SIZE_RET( n )\ 402 IPP_BADARG_RET( (n)<=0, ippStsSizeErr ) 403 404 #define IPP_BAD_STEP_RET( n )\ 405 IPP_BADARG_RET( (n)<=0, ippStsStepErr ) 406 407 #define IPP_BAD_PTR1_RET( ptr )\ 408 IPP_BADARG_RET( NULL==(ptr), ippStsNullPtrErr ) 409 410 #define IPP_BAD_PTR2_RET( ptr1, ptr2 )\ 411 {IPP_BAD_PTR1_RET( ptr1 ); IPP_BAD_PTR1_RET( ptr2 )} 412 413 #define IPP_BAD_PTR3_RET( ptr1, ptr2, ptr3 )\ 414 {IPP_BAD_PTR2_RET( ptr1, ptr2 ); IPP_BAD_PTR1_RET( ptr3 )} 415 416 #define IPP_BAD_PTR4_RET( ptr1, ptr2, ptr3, ptr4 )\ 417 {IPP_BAD_PTR2_RET( ptr1, ptr2 ); IPP_BAD_PTR2_RET( ptr3, ptr4 )} 418 419 #define IPP_BAD_ISIZE_RET(roi) \ 420 IPP_BADARG_RET( ((roi).width<=0 || (roi).height<=0), ippStsSizeErr) 421 422 /* ////////////////////////////////////////////////////////////////////////// */ 423 /* internal messages */ 424 425 #define MSG_LOAD_DLL_ERR (-9700) /* Error at loading of %s library */ 426 #define MSG_NO_DLL (-9701) /* No DLLs were found in the Waterfall procedure */ 427 #define MSG_NO_SHARED (-9702) /* No shared libraries were found in the Waterfall procedure */ 428 429 /* ////////////////////////////////////////////////////////////////////////// */ 430 431 432 typedef union { /* double precision */ 433 Ipp64s hex; 434 Ipp64f fp; 435 } IppFP_64f; 436 437 typedef union { /* single precision */ 438 Ipp32s hex; 439 Ipp32f fp; 440 } IppFP_32f; 441 442 443 /* ////////////////////////////////////////////////////////////////////////// */ 444 445 /* Define NULL pointer value */ 446 #ifndef NULL 447 #ifdef __cplusplus 448 #define NULL 0 449 #else 450 #define NULL ((void *)0) 451 #endif 452 #endif 453 454 #define UNREFERENCED_PARAMETER(p) (void)(p) 455 456 #if defined( _IPP_MARK_LIBRARY ) 457 static char G[] = {73, 80, 80, 71, 101, 110, 117, 105, 110, 101, 243, 193, 210, 207, 215}; 458 #endif 459 460 461 #define STR2(x) #x 462 #define STR(x) STR2(x) 463 #define MESSAGE( desc )\ 464 message(__FILE__ "(" STR(__LINE__) "):" #desc) 465 466 /* 467 // endian definition 468 */ 469 #define IPP_LITTLE_ENDIAN (0) 470 #define IPP_BIG_ENDIAN (1) 471 472 #if defined( _IPP_LE ) 473 #define IPP_ENDIAN IPP_LITTLE_ENDIAN 474 475 #elif defined( _IPP_BE ) 476 #define IPP_ENDIAN IPP_BIG_ENDIAN 477 478 #else 479 #if defined( __ARMEB__ ) 480 #define IPP_ENDIAN IPP_BIG_ENDIAN 481 482 #else 483 #define IPP_ENDIAN IPP_LITTLE_ENDIAN 484 485 #endif 486 #endif 487 488 489 /* ////////////////////////////////////////////////////////////////////////// */ 490 491 /* intrinsics */ 492 #if (_IPP >= _IPP_W7) || (_IPP32E >= _IPP32E_M7) 493 #if defined(__INTEL_COMPILER) || (_MSC_VER >= 1300) 494 #if (_IPP == _IPP_W7) 495 #if defined(__INTEL_COMPILER) 496 #include "emmintrin.h" 497 #else 498 #undef _W7 499 #include "emmintrin.h" 500 #define _W7 501 #endif 502 #define _mm_loadu _mm_loadu_si128 503 #elif (_IPP32E == _IPP32E_M7) 504 #if defined(__INTEL_COMPILER) 505 #include "pmmintrin.h" 506 #define _mm_loadu _mm_lddqu_si128 507 #elif (_MSC_FULL_VER >= 140050110) 508 #include "intrin.h" 509 #define _mm_loadu _mm_lddqu_si128 510 #elif (_MSC_FULL_VER < 140050110) 511 #include "emmintrin.h" 512 #define _mm_loadu _mm_loadu_si128 513 #endif 514 #elif ((_IPP == _IPP_V8) || (_IPP32E == _IPP32E_U8) || (_IPP == _IPP_S8) || (_IPP32E == _IPP32E_N8)) 515 #if defined(__INTEL_COMPILER) 516 #include "tmmintrin.h" 517 #define _mm_loadu _mm_lddqu_si128 518 #elif (_MSC_FULL_VER >= 140050110) 519 #include "intrin.h" 520 #define _mm_loadu _mm_lddqu_si128 521 #elif (_MSC_FULL_VER < 140050110) 522 #include "emmintrin.h" 523 #define _mm_loadu _mm_loadu_si128 524 #endif 525 #elif (_IPP == _IPP_P8) || (_IPP32E == _IPP32E_Y8) 526 #if defined(__INTEL_COMPILER) 527 #include "smmintrin.h" 528 #define _mm_loadu _mm_lddqu_si128 529 #elif (_MSC_FULL_VER >= 140050110) 530 #include "intrin.h" 531 #define _mm_loadu _mm_lddqu_si128 532 #elif (_MSC_FULL_VER < 140050110) 533 #include "emmintrin.h" 534 #define _mm_loadu _mm_loadu_si128 535 #endif 536 #elif (_IPP >= _IPP_G9) || (_IPP32E >= _IPP32E_E9) 537 #if defined(__INTEL_COMPILER) 538 #include "immintrin.h" 539 #define _mm_loadu _mm_lddqu_si128 540 #elif (_MSC_FULL_VER >= 160021003) 541 #include "immintrin.h" 542 #define _mm_loadu _mm_lddqu_si128 543 #endif 544 #endif 545 #endif 546 #endif 547 548 // **** intrinsics for bit casting **** 549 #if defined(__INTEL_COMPILER) 550 extern unsigned int __intel_castf32_u32(float val); 551 extern float __intel_castu32_f32(unsigned int val); 552 extern unsigned __int64 __intel_castf64_u64(double val); 553 extern double __intel_castu64_f64(unsigned __int64 val); 554 #define __CAST_32f32u(val) __intel_castf32_u32((Ipp32f)val) 555 #define __CAST_32u32f(val) __intel_castu32_f32((Ipp32u)val) 556 #define __CAST_64f64u(val) __intel_castf64_u64((Ipp64f)val) 557 #define __CAST_64u64f(val) __intel_castu64_f64((Ipp64u)val) 558 #else 559 #define __CAST_32f32u(val) ( *((Ipp32u*)&val) ) 560 #define __CAST_32u32f(val) ( *((Ipp32f*)&val) ) 561 #define __CAST_64f64u(val) ( *((Ipp64u*)&val) ) 562 #define __CAST_64u64f(val) ( *((Ipp64f*)&val) ) 563 #endif 564 565 566 // short names for vector registers casting 567 #define _pd2ps _mm_castpd_ps 568 #define _ps2pd _mm_castps_pd 569 #define _pd2pi _mm_castpd_si128 570 #define _pi2pd _mm_castsi128_pd 571 #define _ps2pi _mm_castps_si128 572 #define _pi2ps _mm_castsi128_ps 573 574 #define _ypd2ypi _mm256_castpd_si256 575 #define _ypi2ypd _mm256_castsi256_pd 576 #define _yps2ypi _mm256_castps_si256 577 #define _ypi2yps _mm256_castsi256_ps 578 #define _ypd2yps _mm256_castpd_ps 579 #define _yps2ypd _mm256_castps_pd 580 581 #define _yps2ps _mm256_castps256_ps128 582 #define _ypi2pi _mm256_castsi256_si128 583 #define _ypd2pd _mm256_castpd256_pd128 584 #define _ps2yps _mm256_castps128_ps256 585 #define _pi2ypi _mm256_castsi128_si256 586 #define _pd2ypd _mm256_castpd128_pd256 587 588 #define _zpd2zpi _mm512_castpd_si512 589 #define _zpi2zpd _mm512_castsi512_pd 590 #define _zps2zpi _mm512_castps_si512 591 #define _zpi2zps _mm512_castsi512_ps 592 #define _zpd2zps _mm512_castpd_ps 593 #define _zps2zpd _mm512_castps_pd 594 595 #define _zps2ps _mm512_castps512_ps128 596 #define _zpi2pi _mm512_castsi512_si128 597 #define _zpd2pd _mm512_castpd512_pd128 598 #define _ps2zps _mm512_castps128_ps512 599 #define _pi2zpi _mm512_castsi128_si512 600 #define _pd2zpd _mm512_castpd128_pd512 601 602 #define _zps2yps _mm512_castps512_ps256 603 #define _zpi2ypi _mm512_castsi512_si256 604 #define _zpd2ypd _mm512_castpd512_pd256 605 #define _yps2zps _mm512_castps256_ps512 606 #define _ypi2zpi _mm512_castsi256_si512 607 #define _ypd2zpd _mm512_castpd256_pd512 608 609 610 #if defined(__INTEL_COMPILER) 611 #define __IVDEP ivdep 612 #else 613 #define __IVDEP message("message :: 'ivdep' is not defined") 614 #endif 615 616 #if !defined( _MERGED_BLD ) /* compile data if it isn't merged library */ 617 #undef _IPP_DATA 618 #define _IPP_DATA 619 #endif 620 621 622 #if defined( __cplusplus ) 623 } 624 #endif 625 626 #endif /* __OWNDEFS_H__ */ 627 628
