/external/u-boot/drivers/ddr/marvell/a38x/ |
ddr3_init.c | 186 u32 if_id; local 191 &if_id)); 193 CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num));
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ddr3_training_centralization.c | 55 u32 if_id, pattern_id, bit_id; local 79 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { 80 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); 83 (dev_num, ACCESS_TYPE_UNICAST, if_id, 87 (dev_num, ACCESS_TYPE_UNICAST, if_id, 102 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) 496 u32 if_id, pup_id, pattern_id, bit_id; local 697 u32 if_id = 0, bus_id = 0; local [all...] |
ddr3_training_hw_algo.c | 42 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) 53 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 56 CHECK_STATUS(ddr3_tip_if_read(dev_num, access_type, if_id, 59 val = data_read[if_id]; 75 (dev_num, if_id, 99 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 103 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 111 int get_valid_win_rx(u32 dev_num, u32 if_id, u8 res[4]) 124 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id, 160 u32 pup = 0, if_id = 0, num_pup = 0, rep = 0 local 629 u32 if_id = 0; local [all...] |
ddr3_training_pbs.c | 45 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; local 55 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { 56 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); 60 (dev_num, ACCESS_TYPE_UNICAST, if_id, 65 (dev_num, ACCESS_TYPE_UNICAST, if_id, 85 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) 939 u32 data_value = 0, bit = 0, if_id = 0, pup = 0; local 989 u32 if_id, pup, bit; local [all...] |
ddr3_debug.c | 111 u32 if_id, reg_addr, data_value, bus_id; local 119 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { 120 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); 123 if_id, reg_addr, read_data, 125 printf("0x%x ", read_data[if_id]); 133 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) 360 u32 if_id = 0; local 528 u8 if_id = 0, csindex = 0, bus_id = 0, idx = 0; local 691 u32 if_id = 0, bus_id = 0; local 724 u32 if_id = 0, bus_id = 0; local 760 u32 if_id = 0, bus_id = 0; local 787 u32 if_id = 0, bus_id = 0; local 851 u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0; local 906 u32 tmp_val = 0, if_id = 0, pup_id = 0; local 1313 int if_id = 0; local 1460 int if_id = 0, gap = 0; local 1706 u32 seq = 0, if_id = 0, addr, cnt; local [all...] |
ddr3_training_ip_engine.c | 364 ("if_id %d not valid\n", 570 u32 if_id, enum hws_pattern pattern, 582 (dev_num, access_type, if_id, 588 (dev_num, access_type, if_id, 595 (dev_num, access_type, if_id, 601 (dev_num, access_type, if_id, 608 (dev_num, access_type, if_id, 614 (dev_num, access_type, if_id, 624 u32 if_id, enum hws_dir direction, u32 tx_phases, 636 ret = ddr3_tip_if_write(dev_num, access_type, if_id, 847 u32 pattern = 0, if_id; local 874 u32 reg_data, if_id; local 1458 u32 bus_cnt = 0, if_id, dev_num = 0; local 1525 u32 pattern, if_id, pup_id; local [all...] |
ddr3_training_leveling.c | 22 static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id, 24 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id, 29 u32 c_cs, if_id, bus_id; local 37 &if_id)); 45 interface_params[if_id].as_bus_params[bus_id]. 65 u32 bus_num, if_id, cl_val; local 79 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) 80 rl_values[effective_cs][bus_num][if_id] = 0 342 u32 c_cs, if_id, cs_mask = 0; local 383 u32 c_cs, if_id, cs_mask = 0; local 425 u32 bus_num, if_id, cl_val, bit_num; local 833 u32 reg_data = 0, temp = 0, iter, if_id, bus_cnt; local 1203 u32 if_id, bus_id, data, data_tmp; local 1632 u32 bus_id = 0, if_id = 0; local [all...] |
mv_ddr_plat.c | 182 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, 736 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, 743 if (if_id != 0) { 746 if_id)); 854 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr, 868 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr, 1374 u32 if_id, phy_id; local [all...] |
ddr3_training.c | 92 u32 if_id, u32 cl_value, u32 cwl_value); 100 u32 if_id, enum hws_ddr_freq frequency); 102 u32 if_id, enum hws_ddr_freq frequency); 207 static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id); 208 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id); 258 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) 265 data = (tm->interface_params[if_id].bus_width == 268 (dev_num, ACCESS_TYPE_UNICAST, if_id, 271 mem_index = tm->interface_params[if_id].memory_size; 275 (dev_num, ACCESS_TYPE_UNICAST, if_id, 354 u32 if_id; local 1155 u32 data_val = 0, if_id, start_if, end_if; local 1877 u32 if_id; local 1896 u32 if_id, bus_num, cs_bitmask, data_val, cs_num; local 1936 u32 if_id; local 1967 u32 if_id = 0; local 2006 u32 if_id, phy_id, cs; local 2108 u32 if_id, phy_id; local 2141 u32 if_id; local 2609 u32 if_id, stage; local 2678 u32 if_id = 0, mem_mask = 0, bus_index = 0; local [all...] |
/external/u-boot/include/fsl-mc/ |
fsl_dprc.h | 346 MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ 348 MC_CMD_OP(cmd, 1, 32, 32, int, endpoint2->if_id); \ 389 MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint->if_id); \ 412 MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ 435 MC_RSP_OP(cmd, 3, 32, 16, uint16_t, endpoint2->if_id); \ 872 uint16_t if_id; member in struct:dprc_endpoint [all...] |
/external/mesa3d/src/mesa/state_tracker/ |
st_glsl_to_tgsi_temprename.cpp | 618 int if_id = 0; local 671 cur_scope = scopes.create(cur_scope, if_branch, if_id++,
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