| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow_swizzles.c | 106 float imms[4] = {0.0f, 0.0f, 0.0f, 0.0f}; local
389 imms[new_swz] = 0.0f;
393 imms[new_swz] = -0.5f;
395 imms[new_swz] = 0.5f;
400 imms[new_swz] = -1.0f;
402 imms[new_swz] = 1.0f;
406 imms[new_swz] = rc_get_constant_value(c, reg->Index,
412 imms);
|
| /external/capstone/arch/AArch64/ |
| AArch64AddressingModes.h | 125 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
129 // Extract the N, imms, and immr fields.
132 unsigned imms = val & 0x3f; local
136 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
140 unsigned S = imms & (size - 1);
156 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
163 // Extract the N and imms fields needed for checking.
165 unsigned imms = val & 0x3f local
[all...] |
| AArch64InstPrinter.c | 140 int64_t imms = MCOperand_getImm(Op3); local
142 if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
144 shift = 31 - imms;
145 } else if (Opcode == AArch64_UBFMXri && imms != 0x3f &&
146 ((imms + 1 == immr))) {
148 shift = 63 - imms;
149 } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) {
152 } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) {
155 } else if (Opcode == AArch64_SBFMWri && imms == 0x1f)
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| nv50_ir_build_util.h | 192 ImmediateValue *imms[NV50_IR_BUILD_IMM_HT_SIZE]; member in class:nv50_ir::BuildUtil
|
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | 1255 std::vector<int64_t> imms = CreateImmediateValuesBits(\/* imm_bits= *\/ 16, \/* as_uint= *\/ true); local
2656 const uint16_t imms[] = { local
[all...] |
| /external/mesa3d/src/gallium/auxiliary/translate/ |
| translate_sse.c | 473 unsigned imms[2] = { 0, 0x3f800000 }; local
682 imms[swizzle[0] - PIPE_SWIZZLE_0]);
692 imms[swizzle[1] - PIPE_SWIZZLE_0]);
710 imms[swizzle[2] - PIPE_SWIZZLE_0]);
720 imms[swizzle[3] - PIPE_SWIZZLE_0]);
742 unsigned imms[2] = { 0, 1 }; local
798 imms[1] =
826 imms[swizzle[1] - PIPE_SWIZZLE_0]);
833 (imms[swizzle[1] - PIPE_SWIZZLE_0] << 16) |
834 imms[swizzle[0] - PIPE_SWIZZLE_0])
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_shader_internal.h | 94 LLVMValueRef *imms; member in struct:si_shader_context
|
| /art/compiler/utils/ |
| assembler_test.h | 192 std::vector<int64_t> imms = CreateImmediateValuesBits(abs(imm_bits), (imm_bits > 0)); local
196 for (int64_t imm : imms) {
247 std::vector<int64_t> imms = CreateImmediateValuesBits(abs(imm_bits), (imm_bits > 0)); local
252 for (int64_t imm : imms) {
306 std::vector<int64_t> imms = CreateImmediateValuesBits(abs(imm_bits), (imm_bits > 0)); local
308 WarnOnCombinations(reg1_registers.size() * reg2_registers.size() * imms.size());
313 for (int64_t imm : imms) {
360 std::vector<int64_t> imms = CreateImmediateValuesBits(abs(imm_bits), (imm_bits > 0)); local
363 for (int64_t imm : imms) {
563 std::vector<int64_t> imms = CreateImmediateValues(imm_bytes, as_uint) local
1163 std::vector<int64_t> imms = CreateImmediateValues(imm_bytes); local
1446 std::vector<int64_t> imms = CreateImmediateValues(imm_bytes); local
1557 std::vector<int64_t> imms = CreateImmediateValues(imm_bytes); local
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 114 int64_t imms = Op3.getImm(); local
115 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
117 shift = 31 - imms;
118 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
119 ((imms + 1 == immr))) {
121 shift = 63 - imms;
122 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
125 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
128 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f)
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 212 /// the form N:immr:imms.
290 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
293 // Extract the N, imms, and immr fields.
296 unsigned imms = val & 0x3f; local
299 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
303 unsigned S = imms & (size - 1);
318 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
322 // Extract the N and imms fields needed for checking
324 unsigned imms = val & 0x3f; local
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 123 int64_t imms = Op3.getImm(); local
124 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
126 shift = 31 - imms;
127 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
128 ((imms + 1 == immr))) {
130 shift = 63 - imms;
131 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
134 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
137 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 212 /// the form N:immr:imms.
291 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
294 // Extract the N, imms, and immr fields.
297 unsigned imms = val & 0x3f; local
300 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
304 unsigned S = imms & (size - 1);
319 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
323 // Extract the N and imms fields needed for checking
325 unsigned imms = val & 0x3f; local
[all...] |
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_soa.c | 2920 LLVMValueRef imms[4]; local
[all...] |
| /external/v8/src/compiler/ia32/ |
| instruction-selector-ia32.cc | 2421 uint32_t imms[kMaxImms]; local
[all...] |
