| /external/u-boot/arch/x86/lib/ |
| pinctrl_ich6.c | 61 static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
104 /* if iobase is present, let's configure the pad */
105 if (iobase != -1) {
109 * The offset for the same pin for the IOBASE and GPIOBASE are
120 iobase_addr = iobase + pad_offset;
158 u32 iobase = -1; local
169 * IOBASE is used to configure the mode/pads
180 * Get the IOBASE, this is not mandatory as this is not
183 ret = pch_get_io_base(pch, &iobase);
185 debug("%s: invalid IOBASE address (%08x)\n", __func__, iobase)
[all...] |
| /external/u-boot/drivers/rtc/ |
| mvrtc.h | 25 phys_addr_t iobase; member in struct:mvrtc_pdata
|
| /bionic/libc/kernel/uapi/linux/ |
| hdlcdrv.h | 22 int iobase; member in struct:hdlcdrv_params
|
| /external/kernel-headers/original/uapi/linux/ |
| hdlcdrv.h | 17 int iobase; member in struct:hdlcdrv_params
|
| /external/u-boot/drivers/ata/ |
| sata_sil3114.c | 37 static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */ variable
370 u32 port = iobase[5];
654 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
655 pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
656 pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
657 pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
658 pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
659 pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
661 if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) |
[all...] |
| sata_sil.h | 31 ulong iobase[3]; member in struct:sata_info
|
| /external/u-boot/drivers/net/ |
| ftmac100.c | 27 phys_addr_t iobase; member in struct:ftmac100_data
35 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase;
56 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase;
71 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase;
81 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase;
186 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase;
297 dev->iobase = CONFIG_FTMAC100_BASE;
303 priv->iobase = dev->iobase;
398 pdata->iobase = devfdt_get_addr(dev)
[all...] |
| pch_gbe.c | 436 void *iobase; local
448 iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
450 plat->iobase = (ulong)iobase;
451 priv->mac_regs = (struct pch_gbe_regs *)iobase;
|
| pic32_eth.c | 531 void __iomem *iobase; local
542 iobase = ioremap(addr, size);
543 pdata->iobase = (phys_addr_t)addr;
568 priv->ectl_regs = iobase;
569 priv->emac_regs = iobase + PIC32_EMAC1CFG1;
|
| designware.c | 575 dev->iobase = (int)base_addr;
673 u32 iobase = pdata->iobase; local
728 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
729 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
730 iobase = dm_pci_mem_to_phys(dev, iobase);
732 pdata->iobase = iobase;
737 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv)
[all...] |
| sh_eth.c | 628 eth->port_info[eth->port].iobase =
632 dev->iobase = 0;
678 phys_addr_t iobase; member in struct:sh_ether_priv
817 priv->iobase = pdata->iobase;
853 eth->port_info[eth->port].iobase =
895 pdata->iobase = devfdt_get_addr(dev);
|
| dc2114x.c | 175 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
180 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
199 unsigned int iobase; local
256 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
257 iobase &= PCI_BASE_ADDRESS_IO_MASK;
260 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
261 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
263 debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
280 dev->iobase = pci_io_to_phys(devbusfn, iobase);
[all...] |
| ag7xxx.c | 921 void __iomem *iobase, *phyiobase; local
930 iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
933 debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
934 __func__, iobase, phyiobase, priv);
935 priv->regs = iobase;
978 pdata->iobase = devfdt_get_addr(dev);
|
| ravb.c | 123 void __iomem *iobase; member in struct:ravb_priv
154 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
155 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
221 writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
224 return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
242 writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
346 eth->iobase + RAVB_REG_MAHR);
348 writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);
357 writel(0, eth->iobase + RAVB_REG_ECSIPR);
360 writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR)
471 void __iomem *iobase; local
[all...] |
| sni_ave.c | 135 phys_addr_t iobase; member in struct:ave_private
182 return readl(priv->iobase + addr);
206 writel(val, priv->iobase + addr);
245 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
248 mdioctl = readl(priv->iobase + AVE_MDIOCTR);
249 writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR);
251 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
260 return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0);
271 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
274 writel(val, priv->iobase + AVE_MDIOWDR)
[all...] |
| xilinx_axi_emac.c | 91 struct axi_regs *iobase; member in struct:axidma_priv
190 struct axi_regs *regs = priv->iobase;
216 struct axi_regs *regs = priv->iobase;
245 struct axi_regs *regs = priv->iobase;
290 struct axi_regs *regs = priv->iobase;
372 struct axi_regs *regs = priv->iobase;
423 struct axi_regs *regs = priv->iobase;
462 struct axi_regs *regs = priv->iobase;
718 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
719 priv->iobase = (struct axi_regs *)pdata->iobase
[all...] |
| zynq_gem.c | 178 struct zynq_gem_regs *iobase; member in struct:zynq_gem_priv
192 struct zynq_gem_regs *regs = priv->iobase;
288 struct zynq_gem_regs *regs = priv->iobase;
317 struct zynq_gem_regs *regs = priv->iobase;
364 struct zynq_gem_regs *regs = priv->iobase;
488 struct zynq_gem_regs *regs = priv->iobase;
586 struct zynq_gem_regs *regs = priv->iobase;
699 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
700 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
[all...] |
| /device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.10/Modules/_io/ |
| iobase.c | 5 Classes defined here: IOBase, RawIOBase.
17 * IOBase class, an abstract class
25 } iobase;
typedef in typeref:struct:__anon5363
35 "Even though IOBase does not declare read, readinto, or write because\n"
47 "IOBase (and its subclasses) support the iterator protocol, meaning\n"
48 "that an IOBase object can be iterated over yielding the lines in a\n"
51 "IOBase also supports the :keyword:`with` statement. In this example,\n"
58 of the IOBase object rather than the virtual `closed` attribute as returned
171 /* XXX: IOBase thinks it has to maintain its own internal state in
259 iobase_traverse(iobase *self, visitproc visit, void *arg)
[all...] |
| /device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Modules/_io/ |
| iobase.c | 5 Classes defined here: IOBase, RawIOBase.
17 * IOBase class, an abstract class
25 } iobase;
typedef in typeref:struct:__anon5676
35 "Even though IOBase does not declare read, readinto, or write because\n"
47 "IOBase (and its subclasses) support the iterator protocol, meaning\n"
48 "that an IOBase object can be iterated over yielding the lines in a\n"
51 "IOBase also supports the :keyword:`with` statement. In this example,\n"
58 of the IOBase object rather than the virtual `closed` attribute as returned
171 /* XXX: IOBase thinks it has to maintain its own internal state in
259 iobase_traverse(iobase *self, visitproc visit, void *arg)
[all...] |
| /external/python/cpython2/Modules/_io/ |
| iobase.c | 5 Classes defined here: IOBase, RawIOBase.
17 * IOBase class, an abstract class
25 } iobase; typedef in typeref:struct:__anon36642
35 "Even though IOBase does not declare read, readinto, or write because\n"
49 "IOBase (and its subclasses) support the iterator protocol, meaning\n"
50 "that an IOBase object can be iterated over yielding the lines in a\n"
53 "IOBase also supports the :keyword:`with` statement. In this example,\n"
60 of the IOBase object rather than the virtual `closed` attribute as returned
173 /* XXX: IOBase thinks it has to maintain its own internal state in
269 iobase_traverse(iobase *self, visitproc visit, void *arg
[all...] |
| /external/python/cpython3/Modules/_io/ |
| iobase.c | 5 Classes defined here: IOBase, RawIOBase.
24 * IOBase class, an abstract class
32 } iobase; typedef in typeref:struct:__anon37241
42 "Even though IOBase does not declare read, readinto, or write because\n"
56 "IOBase (and its subclasses) support the iterator protocol, meaning\n"
57 "that an IOBase object can be iterated over yielding the lines in a\n"
60 "IOBase also supports the :keyword:`with` statement. In this example,\n"
67 of the IOBase object rather than the virtual `closed` attribute as returned
211 /* XXX: IOBase thinks it has to maintain its own internal state in
315 iobase_traverse(iobase *self, visitproc visit, void *arg
[all...] |
| /external/u-boot/drivers/clk/ |
| clk_pic32.c | 87 void __iomem *iobase; member in struct:pic32_clk_priv
96 v = readl(priv->iobase + SPLLCON);
122 v = readl(priv->iobase + OSCCON);
158 reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10;
193 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20;
237 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20;
400 priv->iobase = ioremap(addr, size);
401 if (!priv->iobase)
|
| /external/u-boot/drivers/pci/ |
| pci_mvebu.c | 73 void __iomem *iobase; member in struct:mvebu_pcie
|
| /external/u-boot/drivers/serial/ |
| serial_sh.h | 8 unsigned long iobase; /* in/out[bwl] */ member in struct:uart_port
|
| /external/u-boot/arch/m68k/include/asm/ |
| fsl_mcdmafec.h | 66 u32 iobase; member in struct:fec_info_dma
|
