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    Searched defs:lcrr (Results 1 - 4 of 4) sorted by null

  /external/u-boot/board/sbc8548/
sbc8548.c 60 uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR; local
68 debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
81 * specifications set LCRR[EADC] to 2 delay cycles.
84 lcrr &= ~LCRR_EADC;
85 lcrr |= LCRR_EADC_2;
93 lcrr &= (~LCRR_DBYP); /* DLL Enabled */
96 lcrr |= LCRR_DBYP; /* DLL Bypass */
98 out_be32(&lbc->lcrr, lcrr);
    [all...]
  /external/u-boot/arch/powerpc/cpu/mpc83xx/
speed.c 83 u32 lcrr; local
392 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
393 switch (lcrr) {
397 lclk_clk = lbiu_clk / lcrr;
400 /* unknown lcrr */
  /external/u-boot/board/socrates/
socrates.c 141 uint lcrr = CONFIG_SYS_LBC_LCRR; local
144 clkdiv = lbc->lcrr & LCRR_CLKDIV;
149 lcrr &= ~LCRR_DBYP; /* DLL Enabled */
151 lcrr |= LCRR_DBYP; /* DLL Bypass */
153 out_be32 (&lbc->lcrr, lcrr);
  /external/u-boot/arch/powerpc/include/asm/
fsl_lbc.h 300 /* LCRR - Clock Ratio Register
471 #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
516 u32 lcrr; /* LBC Clock Ratio */ member in struct:fsl_lbc

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