1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2017 NXP 4 * Copyright 2014-2015 Freescale Semiconductor, Inc. 5 * Layerscape PCIe driver 6 */ 7 8 #include <common.h> 9 #include <asm/arch/fsl_serdes.h> 10 #include <pci.h> 11 #include <asm/io.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <dm.h> 15 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ 16 defined(CONFIG_ARM) 17 #include <asm/arch/clock.h> 18 #endif 19 #include "pcie_layerscape.h" 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 LIST_HEAD(ls_pcie_list); 24 25 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) 26 { 27 return in_le32(pcie->dbi + offset); 28 } 29 30 static void dbi_writel(struct ls_pcie *pcie, unsigned int value, 31 unsigned int offset) 32 { 33 out_le32(pcie->dbi + offset, value); 34 } 35 36 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset) 37 { 38 if (pcie->big_endian) 39 return in_be32(pcie->ctrl + offset); 40 else 41 return in_le32(pcie->ctrl + offset); 42 } 43 44 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value, 45 unsigned int offset) 46 { 47 if (pcie->big_endian) 48 out_be32(pcie->ctrl + offset, value); 49 else 50 out_le32(pcie->ctrl + offset, value); 51 } 52 53 static int ls_pcie_ltssm(struct ls_pcie *pcie) 54 { 55 u32 state; 56 uint svr; 57 58 svr = get_svr(); 59 if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) { 60 state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx)); 61 state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; 62 } else { 63 state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK; 64 } 65 66 return state; 67 } 68 69 static int ls_pcie_link_up(struct ls_pcie *pcie) 70 { 71 int ltssm; 72 73 ltssm = ls_pcie_ltssm(pcie); 74 if (ltssm < LTSSM_PCIE_L0) 75 return 0; 76 77 return 1; 78 } 79 80 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev) 81 { 82 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, 83 PCIE_ATU_VIEWPORT); 84 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET); 85 } 86 87 static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev) 88 { 89 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, 90 PCIE_ATU_VIEWPORT); 91 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET); 92 } 93 94 static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type, 95 u64 phys, u64 bus_addr, pci_size_t size) 96 { 97 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT); 98 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE); 99 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE); 100 dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT); 101 dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET); 102 dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET); 103 dbi_writel(pcie, type, PCIE_ATU_CR1); 104 dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 105 } 106 107 /* Use bar match mode and MEM type as default */ 108 static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, 109 int bar, u64 phys) 110 { 111 dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT); 112 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET); 113 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET); 114 dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); 115 dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | 116 PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2); 117 } 118 119 static void ls_pcie_dump_atu(struct ls_pcie *pcie) 120 { 121 int i; 122 123 for (i = 0; i < PCIE_ATU_REGION_NUM; i++) { 124 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i, 125 PCIE_ATU_VIEWPORT); 126 debug("iATU%d:\n", i); 127 debug("\tLOWER PHYS 0x%08x\n", 128 dbi_readl(pcie, PCIE_ATU_LOWER_BASE)); 129 debug("\tUPPER PHYS 0x%08x\n", 130 dbi_readl(pcie, PCIE_ATU_UPPER_BASE)); 131 debug("\tLOWER BUS 0x%08x\n", 132 dbi_readl(pcie, PCIE_ATU_LOWER_TARGET)); 133 debug("\tUPPER BUS 0x%08x\n", 134 dbi_readl(pcie, PCIE_ATU_UPPER_TARGET)); 135 debug("\tLIMIT 0x%08x\n", 136 readl(pcie->dbi + PCIE_ATU_LIMIT)); 137 debug("\tCR1 0x%08x\n", 138 dbi_readl(pcie, PCIE_ATU_CR1)); 139 debug("\tCR2 0x%08x\n", 140 dbi_readl(pcie, PCIE_ATU_CR2)); 141 } 142 } 143 144 static void ls_pcie_setup_atu(struct ls_pcie *pcie) 145 { 146 struct pci_region *io, *mem, *pref; 147 unsigned long long offset = 0; 148 int idx = 0; 149 uint svr; 150 151 svr = get_svr(); 152 if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) { 153 offset = LS1021_PCIE_SPACE_OFFSET + 154 LS1021_PCIE_SPACE_SIZE * pcie->idx; 155 } 156 157 /* ATU 0 : OUTBOUND : CFG0 */ 158 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, 159 PCIE_ATU_TYPE_CFG0, 160 pcie->cfg_res.start + offset, 161 0, 162 fdt_resource_size(&pcie->cfg_res) / 2); 163 /* ATU 1 : OUTBOUND : CFG1 */ 164 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1, 165 PCIE_ATU_TYPE_CFG1, 166 pcie->cfg_res.start + offset + 167 fdt_resource_size(&pcie->cfg_res) / 2, 168 0, 169 fdt_resource_size(&pcie->cfg_res) / 2); 170 171 pci_get_regions(pcie->bus, &io, &mem, &pref); 172 idx = PCIE_ATU_REGION_INDEX1 + 1; 173 174 /* Fix the pcie memory map for LS2088A series SoCs */ 175 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; 176 if (svr == SVR_LS2088A || svr == SVR_LS2084A || 177 svr == SVR_LS2048A || svr == SVR_LS2044A || 178 svr == SVR_LS2081A || svr == SVR_LS2041A) { 179 if (io) 180 io->phys_start = (io->phys_start & 181 (PCIE_PHYS_SIZE - 1)) + 182 LS2088A_PCIE1_PHYS_ADDR + 183 LS2088A_PCIE_PHYS_SIZE * pcie->idx; 184 if (mem) 185 mem->phys_start = (mem->phys_start & 186 (PCIE_PHYS_SIZE - 1)) + 187 LS2088A_PCIE1_PHYS_ADDR + 188 LS2088A_PCIE_PHYS_SIZE * pcie->idx; 189 if (pref) 190 pref->phys_start = (pref->phys_start & 191 (PCIE_PHYS_SIZE - 1)) + 192 LS2088A_PCIE1_PHYS_ADDR + 193 LS2088A_PCIE_PHYS_SIZE * pcie->idx; 194 } 195 196 if (io) 197 /* ATU : OUTBOUND : IO */ 198 ls_pcie_atu_outbound_set(pcie, idx++, 199 PCIE_ATU_TYPE_IO, 200 io->phys_start + offset, 201 io->bus_start, 202 io->size); 203 204 if (mem) 205 /* ATU : OUTBOUND : MEM */ 206 ls_pcie_atu_outbound_set(pcie, idx++, 207 PCIE_ATU_TYPE_MEM, 208 mem->phys_start + offset, 209 mem->bus_start, 210 mem->size); 211 212 if (pref) 213 /* ATU : OUTBOUND : pref */ 214 ls_pcie_atu_outbound_set(pcie, idx++, 215 PCIE_ATU_TYPE_MEM, 216 pref->phys_start + offset, 217 pref->bus_start, 218 pref->size); 219 220 ls_pcie_dump_atu(pcie); 221 } 222 223 /* Return 0 if the address is valid, -errno if not valid */ 224 static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf) 225 { 226 struct udevice *bus = pcie->bus; 227 228 if (!pcie->enabled) 229 return -ENXIO; 230 231 if (PCI_BUS(bdf) < bus->seq) 232 return -EINVAL; 233 234 if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie))) 235 return -EINVAL; 236 237 if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0)) 238 return -EINVAL; 239 240 return 0; 241 } 242 243 int ls_pcie_conf_address(struct udevice *bus, pci_dev_t bdf, 244 uint offset, void **paddress) 245 { 246 struct ls_pcie *pcie = dev_get_priv(bus); 247 u32 busdev; 248 249 if (ls_pcie_addr_valid(pcie, bdf)) 250 return -EINVAL; 251 252 if (PCI_BUS(bdf) == bus->seq) { 253 *paddress = pcie->dbi + offset; 254 return 0; 255 } 256 257 busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) | 258 PCIE_ATU_DEV(PCI_DEV(bdf)) | 259 PCIE_ATU_FUNC(PCI_FUNC(bdf)); 260 261 if (PCI_BUS(bdf) == bus->seq + 1) { 262 ls_pcie_cfg0_set_busdev(pcie, busdev); 263 *paddress = pcie->cfg0 + offset; 264 } else { 265 ls_pcie_cfg1_set_busdev(pcie, busdev); 266 *paddress = pcie->cfg1 + offset; 267 } 268 return 0; 269 } 270 271 static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf, 272 uint offset, ulong *valuep, 273 enum pci_size_t size) 274 { 275 return pci_generic_mmap_read_config(bus, ls_pcie_conf_address, 276 bdf, offset, valuep, size); 277 } 278 279 static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf, 280 uint offset, ulong value, 281 enum pci_size_t size) 282 { 283 return pci_generic_mmap_write_config(bus, ls_pcie_conf_address, 284 bdf, offset, value, size); 285 } 286 287 /* Clear multi-function bit */ 288 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) 289 { 290 writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE); 291 } 292 293 /* Fix class value */ 294 static void ls_pcie_fix_class(struct ls_pcie *pcie) 295 { 296 writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); 297 } 298 299 /* Drop MSG TLP except for Vendor MSG */ 300 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) 301 { 302 u32 val; 303 304 val = dbi_readl(pcie, PCIE_STRFMR1); 305 val &= 0xDFFFFFFF; 306 dbi_writel(pcie, val, PCIE_STRFMR1); 307 } 308 309 /* Disable all bars in RC mode */ 310 static void ls_pcie_disable_bars(struct ls_pcie *pcie) 311 { 312 u32 sriov; 313 314 sriov = in_le32(pcie->dbi + PCIE_SRIOV); 315 316 /* 317 * TODO: For PCIe controller with SRIOV, the method to disable bars 318 * is different and more complex, so will add later. 319 */ 320 if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) 321 return; 322 323 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0); 324 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1); 325 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1); 326 } 327 328 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie) 329 { 330 ls_pcie_setup_atu(pcie); 331 332 dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN); 333 ls_pcie_fix_class(pcie); 334 ls_pcie_clear_multifunction(pcie); 335 ls_pcie_drop_msg_tlp(pcie); 336 dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN); 337 338 ls_pcie_disable_bars(pcie); 339 } 340 341 static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie) 342 { 343 u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE; 344 345 /* ATU 0 : INBOUND : map BAR0 */ 346 ls_pcie_atu_inbound_set(pcie, 0, 0, phys); 347 /* ATU 1 : INBOUND : map BAR1 */ 348 phys += PCIE_BAR1_SIZE; 349 ls_pcie_atu_inbound_set(pcie, 1, 1, phys); 350 /* ATU 2 : INBOUND : map BAR2 */ 351 phys += PCIE_BAR2_SIZE; 352 ls_pcie_atu_inbound_set(pcie, 2, 2, phys); 353 /* ATU 3 : INBOUND : map BAR4 */ 354 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE; 355 ls_pcie_atu_inbound_set(pcie, 3, 4, phys); 356 357 /* ATU 0 : OUTBOUND : map MEM */ 358 ls_pcie_atu_outbound_set(pcie, 0, 359 PCIE_ATU_TYPE_MEM, 360 pcie->cfg_res.start, 361 0, 362 CONFIG_SYS_PCI_MEMORY_SIZE); 363 } 364 365 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ 366 static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) 367 { 368 /* The least inbound window is 4KiB */ 369 if (size < 4 * 1024) 370 return; 371 372 switch (bar) { 373 case 0: 374 writel(size - 1, bar_base + PCI_BASE_ADDRESS_0); 375 break; 376 case 1: 377 writel(size - 1, bar_base + PCI_BASE_ADDRESS_1); 378 break; 379 case 2: 380 writel(size - 1, bar_base + PCI_BASE_ADDRESS_2); 381 writel(0, bar_base + PCI_BASE_ADDRESS_3); 382 break; 383 case 4: 384 writel(size - 1, bar_base + PCI_BASE_ADDRESS_4); 385 writel(0, bar_base + PCI_BASE_ADDRESS_5); 386 break; 387 default: 388 break; 389 } 390 } 391 392 static void ls_pcie_ep_setup_bars(void *bar_base) 393 { 394 /* BAR0 - 32bit - 4K configuration */ 395 ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); 396 /* BAR1 - 32bit - 8K MSIX*/ 397 ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); 398 /* BAR2 - 64bit - 4K MEM desciptor */ 399 ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); 400 /* BAR4 - 64bit - 1M MEM*/ 401 ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); 402 } 403 404 static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) 405 { 406 ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG); 407 } 408 409 static void ls_pcie_setup_ep(struct ls_pcie *pcie) 410 { 411 u32 sriov; 412 413 sriov = readl(pcie->dbi + PCIE_SRIOV); 414 if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) { 415 int pf, vf; 416 417 for (pf = 0; pf < PCIE_PF_NUM; pf++) { 418 for (vf = 0; vf <= PCIE_VF_NUM; vf++) { 419 ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf), 420 PCIE_PF_VF_CTRL); 421 422 ls_pcie_ep_setup_bars(pcie->dbi); 423 ls_pcie_ep_setup_atu(pcie); 424 } 425 } 426 /* Disable CFG2 */ 427 ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL); 428 } else { 429 ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); 430 ls_pcie_ep_setup_atu(pcie); 431 } 432 433 ls_pcie_ep_enable_cfg(pcie); 434 } 435 436 static int ls_pcie_probe(struct udevice *dev) 437 { 438 struct ls_pcie *pcie = dev_get_priv(dev); 439 const void *fdt = gd->fdt_blob; 440 int node = dev_of_offset(dev); 441 u8 header_type; 442 u16 link_sta; 443 bool ep_mode; 444 uint svr; 445 int ret; 446 fdt_size_t cfg_size; 447 448 pcie->bus = dev; 449 450 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", 451 "dbi", &pcie->dbi_res); 452 if (ret) { 453 printf("ls-pcie: resource \"dbi\" not found\n"); 454 return ret; 455 } 456 457 pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE; 458 459 list_add(&pcie->list, &ls_pcie_list); 460 461 pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)); 462 if (!pcie->enabled) { 463 printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); 464 return 0; 465 } 466 467 pcie->dbi = map_physmem(pcie->dbi_res.start, 468 fdt_resource_size(&pcie->dbi_res), 469 MAP_NOCACHE); 470 471 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", 472 "lut", &pcie->lut_res); 473 if (!ret) 474 pcie->lut = map_physmem(pcie->lut_res.start, 475 fdt_resource_size(&pcie->lut_res), 476 MAP_NOCACHE); 477 478 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", 479 "ctrl", &pcie->ctrl_res); 480 if (!ret) 481 pcie->ctrl = map_physmem(pcie->ctrl_res.start, 482 fdt_resource_size(&pcie->ctrl_res), 483 MAP_NOCACHE); 484 if (!pcie->ctrl) 485 pcie->ctrl = pcie->lut; 486 487 if (!pcie->ctrl) { 488 printf("%s: NOT find CTRL\n", dev->name); 489 return -1; 490 } 491 492 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", 493 "config", &pcie->cfg_res); 494 if (ret) { 495 printf("%s: resource \"config\" not found\n", dev->name); 496 return ret; 497 } 498 499 /* 500 * Fix the pcie memory map address and PF control registers address 501 * for LS2088A series SoCs 502 */ 503 svr = get_svr(); 504 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; 505 if (svr == SVR_LS2088A || svr == SVR_LS2084A || 506 svr == SVR_LS2048A || svr == SVR_LS2044A || 507 svr == SVR_LS2081A || svr == SVR_LS2041A) { 508 cfg_size = fdt_resource_size(&pcie->cfg_res); 509 pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + 510 LS2088A_PCIE_PHYS_SIZE * pcie->idx; 511 pcie->cfg_res.end = pcie->cfg_res.start + cfg_size; 512 pcie->ctrl = pcie->lut + 0x40000; 513 } 514 515 pcie->cfg0 = map_physmem(pcie->cfg_res.start, 516 fdt_resource_size(&pcie->cfg_res), 517 MAP_NOCACHE); 518 pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2; 519 520 pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian"); 521 522 debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n", 523 dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut, 524 (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0, 525 pcie->big_endian); 526 527 header_type = readb(pcie->dbi + PCI_HEADER_TYPE); 528 ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; 529 printf("PCIe%u: %s %s", pcie->idx, dev->name, 530 ep_mode ? "Endpoint" : "Root Complex"); 531 532 if (ep_mode) 533 ls_pcie_setup_ep(pcie); 534 else 535 ls_pcie_setup_ctrl(pcie); 536 537 if (!ls_pcie_link_up(pcie)) { 538 /* Let the user know there's no PCIe link */ 539 printf(": no link\n"); 540 return 0; 541 } 542 543 /* Print the negotiated PCIe link width */ 544 link_sta = readw(pcie->dbi + PCIE_LINK_STA); 545 printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4, 546 link_sta & PCIE_LINK_SPEED_MASK); 547 548 return 0; 549 } 550 551 static const struct dm_pci_ops ls_pcie_ops = { 552 .read_config = ls_pcie_read_config, 553 .write_config = ls_pcie_write_config, 554 }; 555 556 static const struct udevice_id ls_pcie_ids[] = { 557 { .compatible = "fsl,ls-pcie" }, 558 { } 559 }; 560 561 U_BOOT_DRIVER(pci_layerscape) = { 562 .name = "pci_layerscape", 563 .id = UCLASS_PCI, 564 .of_match = ls_pcie_ids, 565 .ops = &ls_pcie_ops, 566 .probe = ls_pcie_probe, 567 .priv_auto_alloc_size = sizeof(struct ls_pcie), 568 }; 569
