1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 4 */ 5 6 #ifndef _RESET_MANAGER_GEN5_H_ 7 #define _RESET_MANAGER_GEN5_H_ 8 9 #include <dt-bindings/reset/altr,rst-mgr.h> 10 11 void reset_deassert_peripherals_handoff(void); 12 void socfpga_bridges_reset(int enable); 13 14 struct socfpga_reset_manager { 15 u32 status; 16 u32 ctrl; 17 u32 counts; 18 u32 padding1; 19 u32 mpu_mod_reset; 20 u32 per_mod_reset; 21 u32 per2_mod_reset; 22 u32 brg_mod_reset; 23 u32 misc_mod_reset; 24 u32 padding2[12]; 25 u32 tstscratch; 26 }; 27 28 /* 29 * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: 30 * 0 ... mpumodrst 31 * 1 ... permodrst 32 * 2 ... per2modrst 33 * 3 ... brgmodrst 34 * 4 ... miscmodrst 35 */ 36 #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) 37 #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) 38 #define RSTMGR_NAND RSTMGR_DEFINE(1, 4) 39 #define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) 40 #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) 41 #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) 42 #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) 43 #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) 44 #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) 45 #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) 46 #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) 47 #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) 48 49 #endif /* _RESET_MANAGER_GEN5_H_ */ 50
