1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Freescale i.MX23/i.MX28 specific functions 4 * 5 * Copyright (C) 2011 Marek Vasut <marek.vasut (at) gmail.com> 6 * on behalf of DENX Software Engineering GmbH 7 */ 8 9 #ifndef __MXS_SYS_PROTO_H__ 10 #define __MXS_SYS_PROTO_H__ 11 12 #include <asm/mach-imx/sys_proto.h> 13 14 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); 15 16 #ifdef CONFIG_SPL_BUILD 17 18 #if defined(CONFIG_MX23) 19 #include <asm/arch/iomux-mx23.h> 20 #elif defined(CONFIG_MX28) 21 #include <asm/arch/iomux-mx28.h> 22 #endif 23 24 void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, 25 const iomux_cfg_t *iomux_setup, 26 const unsigned int iomux_size); 27 28 void mxs_power_switch_dcdc_clocksource(uint32_t freqsel); 29 #endif 30 31 struct mxs_pair { 32 uint8_t boot_pads; 33 uint8_t boot_mask; 34 const char *mode; 35 }; 36 37 static const struct mxs_pair mxs_boot_modes[] = { 38 #if defined(CONFIG_MX23) 39 { 0x00, 0x0f, "USB" }, 40 { 0x01, 0x1f, "I2C, master" }, 41 { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, 42 { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, 43 { 0x04, 0x1f, "NAND" }, 44 { 0x06, 0x1f, "JTAG" }, 45 { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, 46 { 0x09, 0x1f, "SSP SD/MMC #0" }, 47 { 0x0a, 0x1f, "SSP SD/MMC #1" }, 48 { 0x00, 0x00, "Reserved/Unknown/Wrong" }, 49 #elif defined(CONFIG_MX28) 50 { 0x00, 0x0f, "USB #0" }, 51 { 0x01, 0x1f, "I2C #0, master, 3V3" }, 52 { 0x11, 0x1f, "I2C #0, master, 1V8" }, 53 { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, 54 { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, 55 { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, 56 { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, 57 { 0x04, 0x1f, "NAND, 3V3" }, 58 { 0x14, 0x1f, "NAND, 1V8" }, 59 { 0x06, 0x1f, "JTAG" }, 60 { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, 61 { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, 62 { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, 63 { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, 64 { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, 65 { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, 66 { 0x00, 0x00, "Reserved/Unknown/Wrong" }, 67 #endif 68 }; 69 70 #define MXS_BM_USB 0x00 71 #define MXS_BM_I2C_MASTER_3V3 0x01 72 #define MXS_BM_I2C_MASTER_1V8 0x11 73 #define MXS_BM_SPI2_MASTER_3V3_NOR 0x02 74 #define MXS_BM_SPI2_MASTER_1V8_NOR 0x12 75 #define MXS_BM_SPI3_MASTER_3V3_NOR 0x03 76 #define MXS_BM_SPI3_MASTER_1V8_NOR 0x13 77 #define MXS_BM_NAND_3V3 0x04 78 #define MXS_BM_NAND_1V8 0x14 79 #define MXS_BM_JTAG 0x06 80 #define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08 81 #define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18 82 #define MXS_BM_SDMMC0_3V3 0x09 83 #define MXS_BM_SDMMC0_1V8 0x19 84 #define MXS_BM_SDMMC1_3V3 0x0a 85 #define MXS_BM_SDMMC1_1V8 0x1a 86 87 #define MXS_SPL_DATA ((struct mxs_spl_data *)(CONFIG_SYS_TEXT_BASE - 0x200)) 88 89 struct mxs_spl_data { 90 uint8_t boot_mode_idx; 91 uint32_t mem_dram_size; 92 }; 93 94 int mxs_dram_init(void); 95 96 #endif /* __SYS_PROTO_H__ */ 97
