1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Freescale i.MX28 PINCTRL Register Definitions 4 * 5 * Copyright (C) 2011 Marek Vasut <marek.vasut (at) gmail.com> 6 * on behalf of DENX Software Engineering GmbH 7 * 8 * Based on code from LTIB: 9 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 10 */ 11 12 #ifndef __MX28_REGS_PINCTRL_H__ 13 #define __MX28_REGS_PINCTRL_H__ 14 15 #include <asm/mach-imx/regs-common.h> 16 17 #ifndef __ASSEMBLY__ 18 struct mxs_pinctrl_regs { 19 mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */ 20 21 uint32_t reserved1[60]; 22 23 mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ 24 mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ 25 mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ 26 mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ 27 mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ 28 mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ 29 mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ 30 mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ 31 mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ 32 mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ 33 mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ 34 mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ 35 mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ 36 mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ 37 38 uint32_t reserved2[72]; 39 40 mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */ 41 mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */ 42 mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */ 43 mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */ 44 mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */ 45 mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */ 46 mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */ 47 mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */ 48 mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */ 49 mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */ 50 mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ 51 mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ 52 mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ 53 mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ 54 mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ 55 mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ 56 mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */ 57 mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */ 58 mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */ 59 mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */ 60 61 uint32_t reserved3[112]; 62 63 mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */ 64 mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */ 65 mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */ 66 mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */ 67 mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */ 68 mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */ 69 mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */ 70 71 uint32_t reserved4[36]; 72 73 mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */ 74 mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */ 75 mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */ 76 mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */ 77 mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */ 78 79 uint32_t reserved5[108]; 80 81 mxs_reg_32(hw_pinctrl_din0) /* 0x900 */ 82 mxs_reg_32(hw_pinctrl_din1) /* 0x910 */ 83 mxs_reg_32(hw_pinctrl_din2) /* 0x920 */ 84 mxs_reg_32(hw_pinctrl_din3) /* 0x930 */ 85 mxs_reg_32(hw_pinctrl_din4) /* 0x940 */ 86 87 uint32_t reserved6[108]; 88 89 mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */ 90 mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */ 91 mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */ 92 mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */ 93 mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */ 94 95 uint32_t reserved7[300]; 96 97 mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ 98 mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ 99 mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ 100 mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ 101 mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ 102 103 uint32_t reserved8[44]; 104 105 mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ 106 mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ 107 mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ 108 mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ 109 mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ 110 111 uint32_t reserved9[44]; 112 113 mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ 114 mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ 115 mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ 116 mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ 117 mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ 118 119 uint32_t reserved10[44]; 120 121 mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ 122 mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ 123 mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ 124 mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ 125 mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ 126 127 uint32_t reserved11[44]; 128 129 mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ 130 mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ 131 mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ 132 mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ 133 mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ 134 135 uint32_t reserved12[380]; 136 137 mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ 138 139 uint32_t reserved13[76]; 140 141 mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ 142 }; 143 #endif 144 145 #define PINCTRL_CTRL_SFTRST (1 << 31) 146 #define PINCTRL_CTRL_CLKGATE (1 << 30) 147 #define PINCTRL_CTRL_PRESENT4 (1 << 24) 148 #define PINCTRL_CTRL_PRESENT3 (1 << 23) 149 #define PINCTRL_CTRL_PRESENT2 (1 << 22) 150 #define PINCTRL_CTRL_PRESENT1 (1 << 21) 151 #define PINCTRL_CTRL_PRESENT0 (1 << 20) 152 #define PINCTRL_CTRL_IRQOUT4 (1 << 4) 153 #define PINCTRL_CTRL_IRQOUT3 (1 << 3) 154 #define PINCTRL_CTRL_IRQOUT2 (1 << 2) 155 #define PINCTRL_CTRL_IRQOUT1 (1 << 1) 156 #define PINCTRL_CTRL_IRQOUT0 (1 << 0) 157 158 #define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14) 159 #define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14 160 #define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12) 161 #define PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET 12 162 #define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10) 163 #define PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET 10 164 #define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8) 165 #define PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET 8 166 #define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6) 167 #define PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET 6 168 #define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4) 169 #define PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET 4 170 #define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2) 171 #define PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET 2 172 #define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0) 173 #define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0 174 175 #define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24) 176 #define PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET 24 177 #define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22) 178 #define PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET 22 179 #define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20) 180 #define PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET 20 181 #define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18) 182 #define PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET 18 183 #define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16) 184 #define PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET 16 185 #define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14) 186 #define PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET 14 187 #define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12) 188 #define PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET 12 189 #define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10) 190 #define PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET 10 191 #define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8) 192 #define PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET 8 193 #define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6) 194 #define PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET 6 195 #define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4) 196 #define PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET 4 197 #define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2) 198 #define PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET 2 199 #define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0) 200 #define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0 201 202 #define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30) 203 #define PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET 30 204 #define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28) 205 #define PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET 28 206 #define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26) 207 #define PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET 26 208 #define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24) 209 #define PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET 24 210 #define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22) 211 #define PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET 22 212 #define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20) 213 #define PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET 20 214 #define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18) 215 #define PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET 18 216 #define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16) 217 #define PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET 16 218 #define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14) 219 #define PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET 14 220 #define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12) 221 #define PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET 12 222 #define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10) 223 #define PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET 10 224 #define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8) 225 #define PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET 8 226 #define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6) 227 #define PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET 6 228 #define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4) 229 #define PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET 4 230 #define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2) 231 #define PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET 2 232 #define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0) 233 #define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0 234 235 #define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30) 236 #define PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET 30 237 #define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28) 238 #define PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET 28 239 #define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26) 240 #define PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET 26 241 #define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24) 242 #define PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET 24 243 #define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22) 244 #define PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET 22 245 #define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20) 246 #define PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET 20 247 #define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18) 248 #define PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET 18 249 #define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16) 250 #define PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET 16 251 #define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14) 252 #define PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET 14 253 #define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12) 254 #define PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET 12 255 #define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10) 256 #define PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET 10 257 #define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8) 258 #define PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET 8 259 #define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6) 260 #define PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET 6 261 #define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4) 262 #define PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET 4 263 #define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2) 264 #define PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET 2 265 #define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0) 266 #define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0 267 268 #define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30) 269 #define PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET 30 270 #define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28) 271 #define PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET 28 272 #define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26) 273 #define PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET 26 274 #define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24) 275 #define PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET 24 276 #define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20) 277 #define PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET 20 278 #define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18) 279 #define PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET 18 280 #define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16) 281 #define PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET 16 282 #define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14) 283 #define PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET 14 284 #define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12) 285 #define PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET 12 286 #define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10) 287 #define PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET 10 288 #define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8) 289 #define PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET 8 290 #define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6) 291 #define PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET 6 292 #define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4) 293 #define PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET 4 294 #define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2) 295 #define PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET 2 296 #define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0) 297 #define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0 298 299 #define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22) 300 #define PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET 22 301 #define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20) 302 #define PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET 20 303 #define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18) 304 #define PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET 18 305 #define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16) 306 #define PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET 16 307 #define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10) 308 #define PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET 10 309 #define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8) 310 #define PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET 8 311 #define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6) 312 #define PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET 6 313 #define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4) 314 #define PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET 4 315 #define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2) 316 #define PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET 2 317 #define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0) 318 #define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0 319 320 #define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30) 321 #define PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET 30 322 #define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28) 323 #define PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET 28 324 #define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26) 325 #define PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET 26 326 #define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24) 327 #define PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET 24 328 #define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22) 329 #define PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET 22 330 #define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20) 331 #define PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET 20 332 #define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18) 333 #define PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET 18 334 #define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16) 335 #define PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET 16 336 #define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14) 337 #define PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET 14 338 #define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12) 339 #define PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET 12 340 #define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10) 341 #define PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET 10 342 #define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8) 343 #define PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET 8 344 #define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6) 345 #define PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET 6 346 #define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4) 347 #define PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET 4 348 #define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2) 349 #define PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET 2 350 #define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0) 351 #define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0 352 353 #define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28) 354 #define PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET 28 355 #define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26) 356 #define PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET 26 357 #define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24) 358 #define PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET 24 359 #define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22) 360 #define PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET 22 361 #define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20) 362 #define PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET 20 363 #define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18) 364 #define PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET 18 365 #define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16) 366 #define PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET 16 367 #define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14) 368 #define PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET 14 369 #define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12) 370 #define PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET 12 371 #define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10) 372 #define PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET 10 373 #define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8) 374 #define PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET 8 375 #define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4) 376 #define PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET 4 377 #define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2) 378 #define PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET 2 379 #define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0) 380 #define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0 381 382 #define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30) 383 #define PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET 30 384 #define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28) 385 #define PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET 28 386 #define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26) 387 #define PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET 26 388 #define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24) 389 #define PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET 24 390 #define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22) 391 #define PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET 22 392 #define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20) 393 #define PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET 20 394 #define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18) 395 #define PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET 18 396 #define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16) 397 #define PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET 16 398 #define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14) 399 #define PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET 14 400 #define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12) 401 #define PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET 12 402 #define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10) 403 #define PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET 10 404 #define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8) 405 #define PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET 8 406 #define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6) 407 #define PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET 6 408 #define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4) 409 #define PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET 4 410 #define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2) 411 #define PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET 2 412 #define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0) 413 #define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0 414 415 #define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8) 416 #define PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET 8 417 #define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0) 418 #define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0 419 420 #define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30) 421 #define PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET 30 422 #define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28) 423 #define PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET 28 424 #define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26) 425 #define PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET 26 426 #define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24) 427 #define PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET 24 428 #define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22) 429 #define PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET 22 430 #define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20) 431 #define PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET 20 432 #define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18) 433 #define PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET 18 434 #define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16) 435 #define PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET 16 436 #define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14) 437 #define PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET 14 438 #define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12) 439 #define PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET 12 440 #define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10) 441 #define PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET 10 442 #define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8) 443 #define PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET 8 444 #define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6) 445 #define PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET 6 446 #define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4) 447 #define PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET 4 448 #define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2) 449 #define PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET 2 450 #define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0) 451 #define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0 452 453 #define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20) 454 #define PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET 20 455 #define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14) 456 #define PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET 14 457 #define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12) 458 #define PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET 12 459 #define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10) 460 #define PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET 10 461 #define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8) 462 #define PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET 8 463 #define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6) 464 #define PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET 6 465 #define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4) 466 #define PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET 4 467 #define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2) 468 #define PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET 2 469 #define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0) 470 #define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0 471 472 #define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28) 473 #define PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET 28 474 #define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26) 475 #define PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET 26 476 #define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24) 477 #define PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET 24 478 #define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22) 479 #define PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET 22 480 #define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20) 481 #define PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET 20 482 #define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18) 483 #define PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET 18 484 #define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16) 485 #define PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET 16 486 #define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14) 487 #define PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET 14 488 #define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12) 489 #define PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET 12 490 #define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10) 491 #define PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET 10 492 #define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8) 493 #define PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET 8 494 #define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6) 495 #define PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET 6 496 #define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4) 497 #define PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET 4 498 #define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2) 499 #define PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET 2 500 #define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0) 501 #define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0 502 503 #define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16) 504 #define PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET 16 505 #define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14) 506 #define PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET 14 507 #define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12) 508 #define PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET 12 509 #define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10) 510 #define PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET 10 511 #define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8) 512 #define PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET 8 513 #define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6) 514 #define PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET 6 515 #define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4) 516 #define PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET 4 517 #define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2) 518 #define PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET 2 519 #define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0) 520 #define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0 521 522 #define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30) 523 #define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28) 524 #define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28 525 #define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26) 526 #define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24) 527 #define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24 528 #define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22) 529 #define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20) 530 #define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20 531 #define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18) 532 #define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16) 533 #define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16 534 #define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14) 535 #define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12) 536 #define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12 537 #define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10) 538 #define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8) 539 #define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8 540 #define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6) 541 #define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4) 542 #define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4 543 #define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2) 544 #define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0) 545 #define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0 546 547 #define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30) 548 #define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28) 549 #define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28 550 #define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26) 551 #define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24) 552 #define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24 553 #define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22) 554 #define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20) 555 #define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20 556 #define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18) 557 #define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16) 558 #define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16 559 #define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14) 560 #define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12) 561 #define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12 562 #define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10) 563 #define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8) 564 #define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8 565 #define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6) 566 #define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4) 567 #define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4 568 #define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2) 569 #define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0) 570 #define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0 571 572 #define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18) 573 #define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16) 574 #define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16 575 #define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14) 576 #define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12) 577 #define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12 578 #define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10) 579 #define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8) 580 #define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8 581 #define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6) 582 #define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4) 583 #define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4 584 #define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2) 585 #define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0) 586 #define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0 587 588 #define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30) 589 #define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28) 590 #define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28 591 #define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26) 592 #define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24) 593 #define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24 594 #define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22) 595 #define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20) 596 #define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20 597 #define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18) 598 #define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16) 599 #define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16 600 #define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14) 601 #define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12) 602 #define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12 603 #define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10) 604 #define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8) 605 #define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8 606 #define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6) 607 #define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4) 608 #define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4 609 #define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2) 610 #define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0) 611 #define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0 612 613 #define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30) 614 #define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28) 615 #define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28 616 #define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26) 617 #define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24) 618 #define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24 619 #define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22) 620 #define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20) 621 #define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20 622 #define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18) 623 #define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16) 624 #define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16 625 #define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14) 626 #define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12) 627 #define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12 628 #define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10) 629 #define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8) 630 #define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8 631 #define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6) 632 #define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4) 633 #define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4 634 #define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2) 635 #define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0) 636 #define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0 637 638 #define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30) 639 #define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28) 640 #define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28 641 #define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26) 642 #define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24) 643 #define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24 644 #define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22) 645 #define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20) 646 #define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20 647 #define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18) 648 #define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16) 649 #define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16 650 #define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14) 651 #define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12) 652 #define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12 653 #define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10) 654 #define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8) 655 #define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8 656 #define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6) 657 #define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4) 658 #define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4 659 #define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2) 660 #define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0) 661 #define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0 662 663 #define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30) 664 #define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28) 665 #define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28 666 #define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26) 667 #define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24) 668 #define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24 669 #define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22) 670 #define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20) 671 #define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20 672 #define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18) 673 #define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16) 674 #define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16 675 #define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14) 676 #define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12) 677 #define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12 678 #define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10) 679 #define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8) 680 #define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8 681 #define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6) 682 #define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4) 683 #define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4 684 #define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2) 685 #define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0) 686 #define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0 687 688 #define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30) 689 #define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28) 690 #define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28 691 #define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26) 692 #define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24) 693 #define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24 694 #define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22) 695 #define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20) 696 #define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20 697 #define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18) 698 #define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16) 699 #define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16 700 #define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14) 701 #define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12) 702 #define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12 703 #define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10) 704 #define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8) 705 #define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8 706 #define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6) 707 #define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4) 708 #define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4 709 #define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2) 710 #define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0) 711 #define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0 712 713 #define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30) 714 #define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28) 715 #define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28 716 #define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26) 717 #define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24) 718 #define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24 719 #define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22) 720 #define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20) 721 #define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20 722 #define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18) 723 #define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16) 724 #define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16 725 #define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10) 726 #define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8) 727 #define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8 728 #define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6) 729 #define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4) 730 #define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4 731 #define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2) 732 #define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0) 733 #define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0 734 735 #define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22) 736 #define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20) 737 #define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20 738 #define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18) 739 #define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16) 740 #define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16 741 #define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14) 742 #define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12) 743 #define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12 744 #define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10) 745 #define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8) 746 #define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8 747 #define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6) 748 #define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4) 749 #define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4 750 #define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2) 751 #define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0) 752 #define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0 753 754 #define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14) 755 #define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12) 756 #define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12 757 #define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10) 758 #define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8) 759 #define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8 760 #define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6) 761 #define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4) 762 #define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4 763 #define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2) 764 #define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0) 765 #define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0 766 767 #define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30) 768 #define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28) 769 #define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28 770 #define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26) 771 #define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24) 772 #define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24 773 #define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22) 774 #define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20) 775 #define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20 776 #define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18) 777 #define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16) 778 #define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16 779 #define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14) 780 #define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12) 781 #define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12 782 #define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10) 783 #define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8) 784 #define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8 785 #define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6) 786 #define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4) 787 #define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4 788 #define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2) 789 #define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0) 790 #define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0 791 792 #define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30) 793 #define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28) 794 #define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28 795 #define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26) 796 #define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24) 797 #define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24 798 #define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22) 799 #define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20) 800 #define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20 801 #define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18) 802 #define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16) 803 #define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16 804 #define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14) 805 #define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12) 806 #define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12 807 #define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10) 808 #define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8) 809 #define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8 810 #define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6) 811 #define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4) 812 #define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4 813 #define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2) 814 #define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0) 815 #define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0 816 817 #define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30) 818 #define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28) 819 #define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28 820 #define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26) 821 #define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24) 822 #define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24 823 #define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22) 824 #define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20) 825 #define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20 826 #define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18) 827 #define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16) 828 #define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16 829 #define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10) 830 #define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8) 831 #define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8 832 #define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6) 833 #define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4) 834 #define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4 835 #define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2) 836 #define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0) 837 #define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0 838 839 #define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26) 840 #define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24) 841 #define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24 842 #define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22) 843 #define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20) 844 #define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20 845 #define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18) 846 #define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16) 847 #define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16 848 #define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14) 849 #define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12) 850 #define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12 851 #define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10) 852 #define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8) 853 #define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8 854 #define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6) 855 #define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4) 856 #define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4 857 #define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2) 858 #define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0) 859 #define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0 860 861 #define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30) 862 #define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28) 863 #define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28 864 #define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26) 865 #define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24) 866 #define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24 867 #define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22) 868 #define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20) 869 #define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20 870 #define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18) 871 #define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16) 872 #define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16 873 #define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14) 874 #define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12) 875 #define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12 876 #define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10) 877 #define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8) 878 #define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8 879 #define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6) 880 #define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4) 881 #define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4 882 #define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2) 883 #define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0) 884 #define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0 885 886 #define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30) 887 #define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28) 888 #define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28 889 #define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26) 890 #define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24) 891 #define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24 892 #define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22) 893 #define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20) 894 #define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20 895 #define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18) 896 #define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16) 897 #define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16 898 #define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14) 899 #define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12) 900 #define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12 901 #define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10) 902 #define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8) 903 #define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8 904 #define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6) 905 #define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4) 906 #define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4 907 #define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2) 908 #define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0) 909 #define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0 910 911 #define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18) 912 #define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16) 913 #define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16 914 #define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2) 915 #define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0) 916 #define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0 917 918 #define PINCTRL_PULL0_BANK0_PIN28 (1 << 28) 919 #define PINCTRL_PULL0_BANK0_PIN27 (1 << 27) 920 #define PINCTRL_PULL0_BANK0_PIN26 (1 << 26) 921 #define PINCTRL_PULL0_BANK0_PIN25 (1 << 25) 922 #define PINCTRL_PULL0_BANK0_PIN24 (1 << 24) 923 #define PINCTRL_PULL0_BANK0_PIN23 (1 << 23) 924 #define PINCTRL_PULL0_BANK0_PIN22 (1 << 22) 925 #define PINCTRL_PULL0_BANK0_PIN21 (1 << 21) 926 #define PINCTRL_PULL0_BANK0_PIN20 (1 << 20) 927 #define PINCTRL_PULL0_BANK0_PIN19 (1 << 19) 928 #define PINCTRL_PULL0_BANK0_PIN18 (1 << 18) 929 #define PINCTRL_PULL0_BANK0_PIN17 (1 << 17) 930 #define PINCTRL_PULL0_BANK0_PIN16 (1 << 16) 931 #define PINCTRL_PULL0_BANK0_PIN07 (1 << 7) 932 #define PINCTRL_PULL0_BANK0_PIN06 (1 << 6) 933 #define PINCTRL_PULL0_BANK0_PIN05 (1 << 5) 934 #define PINCTRL_PULL0_BANK0_PIN04 (1 << 4) 935 #define PINCTRL_PULL0_BANK0_PIN03 (1 << 3) 936 #define PINCTRL_PULL0_BANK0_PIN02 (1 << 2) 937 #define PINCTRL_PULL0_BANK0_PIN01 (1 << 1) 938 #define PINCTRL_PULL0_BANK0_PIN00 (1 << 0) 939 940 #define PINCTRL_PULL1_BANK1_PIN31 (1 << 31) 941 #define PINCTRL_PULL1_BANK1_PIN30 (1 << 30) 942 #define PINCTRL_PULL1_BANK1_PIN29 (1 << 29) 943 #define PINCTRL_PULL1_BANK1_PIN28 (1 << 28) 944 #define PINCTRL_PULL1_BANK1_PIN27 (1 << 27) 945 #define PINCTRL_PULL1_BANK1_PIN26 (1 << 26) 946 #define PINCTRL_PULL1_BANK1_PIN25 (1 << 25) 947 #define PINCTRL_PULL1_BANK1_PIN24 (1 << 24) 948 #define PINCTRL_PULL1_BANK1_PIN23 (1 << 23) 949 #define PINCTRL_PULL1_BANK1_PIN22 (1 << 22) 950 #define PINCTRL_PULL1_BANK1_PIN21 (1 << 21) 951 #define PINCTRL_PULL1_BANK1_PIN20 (1 << 20) 952 #define PINCTRL_PULL1_BANK1_PIN19 (1 << 19) 953 #define PINCTRL_PULL1_BANK1_PIN18 (1 << 18) 954 #define PINCTRL_PULL1_BANK1_PIN17 (1 << 17) 955 #define PINCTRL_PULL1_BANK1_PIN16 (1 << 16) 956 #define PINCTRL_PULL1_BANK1_PIN15 (1 << 15) 957 #define PINCTRL_PULL1_BANK1_PIN14 (1 << 14) 958 #define PINCTRL_PULL1_BANK1_PIN13 (1 << 13) 959 #define PINCTRL_PULL1_BANK1_PIN12 (1 << 12) 960 #define PINCTRL_PULL1_BANK1_PIN11 (1 << 11) 961 #define PINCTRL_PULL1_BANK1_PIN10 (1 << 10) 962 #define PINCTRL_PULL1_BANK1_PIN09 (1 << 9) 963 #define PINCTRL_PULL1_BANK1_PIN08 (1 << 8) 964 #define PINCTRL_PULL1_BANK1_PIN07 (1 << 7) 965 #define PINCTRL_PULL1_BANK1_PIN06 (1 << 6) 966 #define PINCTRL_PULL1_BANK1_PIN05 (1 << 5) 967 #define PINCTRL_PULL1_BANK1_PIN04 (1 << 4) 968 #define PINCTRL_PULL1_BANK1_PIN03 (1 << 3) 969 #define PINCTRL_PULL1_BANK1_PIN02 (1 << 2) 970 #define PINCTRL_PULL1_BANK1_PIN01 (1 << 1) 971 #define PINCTRL_PULL1_BANK1_PIN00 (1 << 0) 972 973 #define PINCTRL_PULL2_BANK2_PIN27 (1 << 27) 974 #define PINCTRL_PULL2_BANK2_PIN26 (1 << 26) 975 #define PINCTRL_PULL2_BANK2_PIN25 (1 << 25) 976 #define PINCTRL_PULL2_BANK2_PIN24 (1 << 24) 977 #define PINCTRL_PULL2_BANK2_PIN21 (1 << 21) 978 #define PINCTRL_PULL2_BANK2_PIN20 (1 << 20) 979 #define PINCTRL_PULL2_BANK2_PIN19 (1 << 19) 980 #define PINCTRL_PULL2_BANK2_PIN18 (1 << 18) 981 #define PINCTRL_PULL2_BANK2_PIN17 (1 << 17) 982 #define PINCTRL_PULL2_BANK2_PIN16 (1 << 16) 983 #define PINCTRL_PULL2_BANK2_PIN15 (1 << 15) 984 #define PINCTRL_PULL2_BANK2_PIN14 (1 << 14) 985 #define PINCTRL_PULL2_BANK2_PIN13 (1 << 13) 986 #define PINCTRL_PULL2_BANK2_PIN12 (1 << 12) 987 #define PINCTRL_PULL2_BANK2_PIN10 (1 << 10) 988 #define PINCTRL_PULL2_BANK2_PIN09 (1 << 9) 989 #define PINCTRL_PULL2_BANK2_PIN08 (1 << 8) 990 #define PINCTRL_PULL2_BANK2_PIN07 (1 << 7) 991 #define PINCTRL_PULL2_BANK2_PIN06 (1 << 6) 992 #define PINCTRL_PULL2_BANK2_PIN05 (1 << 5) 993 #define PINCTRL_PULL2_BANK2_PIN04 (1 << 4) 994 #define PINCTRL_PULL2_BANK2_PIN03 (1 << 3) 995 #define PINCTRL_PULL2_BANK2_PIN02 (1 << 2) 996 #define PINCTRL_PULL2_BANK2_PIN01 (1 << 1) 997 #define PINCTRL_PULL2_BANK2_PIN00 (1 << 0) 998 999 #define PINCTRL_PULL3_BANK3_PIN30 (1 << 30) 1000 #define PINCTRL_PULL3_BANK3_PIN29 (1 << 29) 1001 #define PINCTRL_PULL3_BANK3_PIN28 (1 << 28) 1002 #define PINCTRL_PULL3_BANK3_PIN27 (1 << 27) 1003 #define PINCTRL_PULL3_BANK3_PIN26 (1 << 26) 1004 #define PINCTRL_PULL3_BANK3_PIN25 (1 << 25) 1005 #define PINCTRL_PULL3_BANK3_PIN24 (1 << 24) 1006 #define PINCTRL_PULL3_BANK3_PIN23 (1 << 23) 1007 #define PINCTRL_PULL3_BANK3_PIN22 (1 << 22) 1008 #define PINCTRL_PULL3_BANK3_PIN21 (1 << 21) 1009 #define PINCTRL_PULL3_BANK3_PIN20 (1 << 20) 1010 #define PINCTRL_PULL3_BANK3_PIN18 (1 << 18) 1011 #define PINCTRL_PULL3_BANK3_PIN17 (1 << 17) 1012 #define PINCTRL_PULL3_BANK3_PIN16 (1 << 16) 1013 #define PINCTRL_PULL3_BANK3_PIN15 (1 << 15) 1014 #define PINCTRL_PULL3_BANK3_PIN14 (1 << 14) 1015 #define PINCTRL_PULL3_BANK3_PIN13 (1 << 13) 1016 #define PINCTRL_PULL3_BANK3_PIN12 (1 << 12) 1017 #define PINCTRL_PULL3_BANK3_PIN11 (1 << 11) 1018 #define PINCTRL_PULL3_BANK3_PIN10 (1 << 10) 1019 #define PINCTRL_PULL3_BANK3_PIN09 (1 << 9) 1020 #define PINCTRL_PULL3_BANK3_PIN08 (1 << 8) 1021 #define PINCTRL_PULL3_BANK3_PIN07 (1 << 7) 1022 #define PINCTRL_PULL3_BANK3_PIN06 (1 << 6) 1023 #define PINCTRL_PULL3_BANK3_PIN05 (1 << 5) 1024 #define PINCTRL_PULL3_BANK3_PIN04 (1 << 4) 1025 #define PINCTRL_PULL3_BANK3_PIN03 (1 << 3) 1026 #define PINCTRL_PULL3_BANK3_PIN02 (1 << 2) 1027 #define PINCTRL_PULL3_BANK3_PIN01 (1 << 1) 1028 #define PINCTRL_PULL3_BANK3_PIN00 (1 << 0) 1029 1030 #define PINCTRL_PULL4_BANK4_PIN20 (1 << 20) 1031 #define PINCTRL_PULL4_BANK4_PIN16 (1 << 16) 1032 #define PINCTRL_PULL4_BANK4_PIN15 (1 << 15) 1033 #define PINCTRL_PULL4_BANK4_PIN14 (1 << 14) 1034 #define PINCTRL_PULL4_BANK4_PIN13 (1 << 13) 1035 #define PINCTRL_PULL4_BANK4_PIN12 (1 << 12) 1036 #define PINCTRL_PULL4_BANK4_PIN11 (1 << 11) 1037 #define PINCTRL_PULL4_BANK4_PIN10 (1 << 10) 1038 #define PINCTRL_PULL4_BANK4_PIN09 (1 << 9) 1039 #define PINCTRL_PULL4_BANK4_PIN08 (1 << 8) 1040 #define PINCTRL_PULL4_BANK4_PIN07 (1 << 7) 1041 #define PINCTRL_PULL4_BANK4_PIN06 (1 << 6) 1042 #define PINCTRL_PULL4_BANK4_PIN05 (1 << 5) 1043 #define PINCTRL_PULL4_BANK4_PIN04 (1 << 4) 1044 #define PINCTRL_PULL4_BANK4_PIN03 (1 << 3) 1045 #define PINCTRL_PULL4_BANK4_PIN02 (1 << 2) 1046 #define PINCTRL_PULL4_BANK4_PIN01 (1 << 1) 1047 #define PINCTRL_PULL4_BANK4_PIN00 (1 << 0) 1048 1049 #define PINCTRL_PULL5_BANK5_PIN26 (1 << 26) 1050 #define PINCTRL_PULL5_BANK5_PIN23 (1 << 23) 1051 #define PINCTRL_PULL5_BANK5_PIN22 (1 << 22) 1052 #define PINCTRL_PULL5_BANK5_PIN21 (1 << 21) 1053 #define PINCTRL_PULL5_BANK5_PIN20 (1 << 20) 1054 #define PINCTRL_PULL5_BANK5_PIN19 (1 << 19) 1055 #define PINCTRL_PULL5_BANK5_PIN18 (1 << 18) 1056 #define PINCTRL_PULL5_BANK5_PIN17 (1 << 17) 1057 #define PINCTRL_PULL5_BANK5_PIN16 (1 << 16) 1058 #define PINCTRL_PULL5_BANK5_PIN15 (1 << 15) 1059 #define PINCTRL_PULL5_BANK5_PIN14 (1 << 14) 1060 #define PINCTRL_PULL5_BANK5_PIN13 (1 << 13) 1061 #define PINCTRL_PULL5_BANK5_PIN12 (1 << 12) 1062 #define PINCTRL_PULL5_BANK5_PIN11 (1 << 11) 1063 #define PINCTRL_PULL5_BANK5_PIN10 (1 << 10) 1064 #define PINCTRL_PULL5_BANK5_PIN09 (1 << 9) 1065 #define PINCTRL_PULL5_BANK5_PIN08 (1 << 8) 1066 #define PINCTRL_PULL5_BANK5_PIN07 (1 << 7) 1067 #define PINCTRL_PULL5_BANK5_PIN06 (1 << 6) 1068 #define PINCTRL_PULL5_BANK5_PIN05 (1 << 5) 1069 #define PINCTRL_PULL5_BANK5_PIN04 (1 << 4) 1070 #define PINCTRL_PULL5_BANK5_PIN03 (1 << 3) 1071 #define PINCTRL_PULL5_BANK5_PIN02 (1 << 2) 1072 #define PINCTRL_PULL5_BANK5_PIN01 (1 << 1) 1073 #define PINCTRL_PULL5_BANK5_PIN00 (1 << 0) 1074 1075 #define PINCTRL_PULL6_BANK6_PIN24 (1 << 24) 1076 #define PINCTRL_PULL6_BANK6_PIN23 (1 << 23) 1077 #define PINCTRL_PULL6_BANK6_PIN22 (1 << 22) 1078 #define PINCTRL_PULL6_BANK6_PIN21 (1 << 21) 1079 #define PINCTRL_PULL6_BANK6_PIN20 (1 << 20) 1080 #define PINCTRL_PULL6_BANK6_PIN19 (1 << 19) 1081 #define PINCTRL_PULL6_BANK6_PIN18 (1 << 18) 1082 #define PINCTRL_PULL6_BANK6_PIN17 (1 << 17) 1083 #define PINCTRL_PULL6_BANK6_PIN16 (1 << 16) 1084 #define PINCTRL_PULL6_BANK6_PIN14 (1 << 14) 1085 #define PINCTRL_PULL6_BANK6_PIN13 (1 << 13) 1086 #define PINCTRL_PULL6_BANK6_PIN12 (1 << 12) 1087 #define PINCTRL_PULL6_BANK6_PIN11 (1 << 11) 1088 #define PINCTRL_PULL6_BANK6_PIN10 (1 << 10) 1089 #define PINCTRL_PULL6_BANK6_PIN09 (1 << 9) 1090 #define PINCTRL_PULL6_BANK6_PIN08 (1 << 8) 1091 #define PINCTRL_PULL6_BANK6_PIN07 (1 << 7) 1092 #define PINCTRL_PULL6_BANK6_PIN06 (1 << 6) 1093 #define PINCTRL_PULL6_BANK6_PIN05 (1 << 5) 1094 #define PINCTRL_PULL6_BANK6_PIN04 (1 << 4) 1095 #define PINCTRL_PULL6_BANK6_PIN03 (1 << 3) 1096 #define PINCTRL_PULL6_BANK6_PIN02 (1 << 2) 1097 #define PINCTRL_PULL6_BANK6_PIN01 (1 << 1) 1098 #define PINCTRL_PULL6_BANK6_PIN00 (1 << 0) 1099 1100 #define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff 1101 #define PINCTRL_DOUT0_DOUT_OFFSET 0 1102 1103 #define PINCTRL_DOUT1_DOUT_MASK 0xffffffff 1104 #define PINCTRL_DOUT1_DOUT_OFFSET 0 1105 1106 #define PINCTRL_DOUT2_DOUT_MASK 0xfffffff 1107 #define PINCTRL_DOUT2_DOUT_OFFSET 0 1108 1109 #define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff 1110 #define PINCTRL_DOUT3_DOUT_OFFSET 0 1111 1112 #define PINCTRL_DOUT4_DOUT_MASK 0x1fffff 1113 #define PINCTRL_DOUT4_DOUT_OFFSET 0 1114 1115 #define PINCTRL_DIN0_DIN_MASK 0x1fffffff 1116 #define PINCTRL_DIN0_DIN_OFFSET 0 1117 1118 #define PINCTRL_DIN1_DIN_MASK 0xffffffff 1119 #define PINCTRL_DIN1_DIN_OFFSET 0 1120 1121 #define PINCTRL_DIN2_DIN_MASK 0xfffffff 1122 #define PINCTRL_DIN2_DIN_OFFSET 0 1123 1124 #define PINCTRL_DIN3_DIN_MASK 0x7fffffff 1125 #define PINCTRL_DIN3_DIN_OFFSET 0 1126 1127 #define PINCTRL_DIN4_DIN_MASK 0x1fffff 1128 #define PINCTRL_DIN4_DIN_OFFSET 0 1129 1130 #define PINCTRL_DOE0_DOE_MASK 0x1fffffff 1131 #define PINCTRL_DOE0_DOE_OFFSET 0 1132 1133 #define PINCTRL_DOE1_DOE_MASK 0xffffffff 1134 #define PINCTRL_DOE1_DOE_OFFSET 0 1135 1136 #define PINCTRL_DOE2_DOE_MASK 0xfffffff 1137 #define PINCTRL_DOE2_DOE_OFFSET 0 1138 1139 #define PINCTRL_DOE3_DOE_MASK 0x7fffffff 1140 #define PINCTRL_DOE3_DOE_OFFSET 0 1141 1142 #define PINCTRL_DOE4_DOE_MASK 0x1fffff 1143 #define PINCTRL_DOE4_DOE_OFFSET 0 1144 1145 #define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff 1146 #define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0 1147 1148 #define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff 1149 #define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0 1150 1151 #define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff 1152 #define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0 1153 1154 #define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff 1155 #define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0 1156 1157 #define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff 1158 #define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0 1159 1160 #define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff 1161 #define PINCTRL_IRQEN0_IRQEN_OFFSET 0 1162 1163 #define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff 1164 #define PINCTRL_IRQEN1_IRQEN_OFFSET 0 1165 1166 #define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff 1167 #define PINCTRL_IRQEN2_IRQEN_OFFSET 0 1168 1169 #define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff 1170 #define PINCTRL_IRQEN3_IRQEN_OFFSET 0 1171 1172 #define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff 1173 #define PINCTRL_IRQEN4_IRQEN_OFFSET 0 1174 1175 #define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff 1176 #define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0 1177 1178 #define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff 1179 #define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0 1180 1181 #define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff 1182 #define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0 1183 1184 #define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff 1185 #define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0 1186 1187 #define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff 1188 #define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0 1189 1190 #define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff 1191 #define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0 1192 1193 #define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff 1194 #define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0 1195 1196 #define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff 1197 #define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0 1198 1199 #define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff 1200 #define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0 1201 1202 #define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff 1203 #define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0 1204 1205 #define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff 1206 #define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0 1207 1208 #define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff 1209 #define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0 1210 1211 #define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff 1212 #define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0 1213 1214 #define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff 1215 #define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0 1216 1217 #define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff 1218 #define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0 1219 1220 #define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26) 1221 #define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET 26 1222 #define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24) 1223 #define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET 24 1224 #define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22) 1225 #define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET 22 1226 #define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20) 1227 #define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET 20 1228 #define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18) 1229 #define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET 18 1230 #define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16) 1231 #define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET 16 1232 #define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14) 1233 #define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET 14 1234 #define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12) 1235 #define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET 12 1236 #define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10) 1237 #define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET 10 1238 #define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8) 1239 #define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET 8 1240 #define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6) 1241 #define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET 6 1242 #define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4) 1243 #define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET 4 1244 #define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2) 1245 #define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET 2 1246 #define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0) 1247 #define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0 1248 1249 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16) 1250 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET 16 1251 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16) 1252 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16) 1253 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16) 1254 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16) 1255 #define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12) 1256 #define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET 12 1257 #define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10) 1258 #define PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET 10 1259 #define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8) 1260 #define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET 8 1261 #define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6) 1262 #define PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET 6 1263 #define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4) 1264 #define PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET 4 1265 #define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2) 1266 #define PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET 2 1267 #define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0) 1268 #define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0 1269 1270 #endif /* __MX28_REGS_PINCTRL_H__ */ 1271
