1 /* 2 * NAND Flash Driver 3 * 4 * Copyright (C) 2006-2014 Texas Instruments. 5 * 6 * Based on Linux DaVinci NAND driver by TI. 7 */ 8 9 #ifndef _DAVINCI_NAND_H_ 10 #define _DAVINCI_NAND_H_ 11 12 #include <linux/mtd/rawnand.h> 13 #include <asm/arch/hardware.h> 14 15 #define NAND_READ_START 0x00 16 #define NAND_READ_END 0x30 17 #define NAND_STATUS 0x70 18 19 #define MASK_CLE 0x10 20 #define MASK_ALE 0x08 21 22 #ifdef CONFIG_SYS_NAND_MASK_CLE 23 #undef MASK_CLE 24 #define MASK_CLE CONFIG_SYS_NAND_MASK_CLE 25 #endif 26 #ifdef CONFIG_SYS_NAND_MASK_ALE 27 #undef MASK_ALE 28 #define MASK_ALE CONFIG_SYS_NAND_MASK_ALE 29 #endif 30 31 struct davinci_emif_regs { 32 uint32_t ercsr; 33 uint32_t awccr; 34 uint32_t sdbcr; 35 uint32_t sdrcr; 36 union { 37 uint32_t abncr[4]; 38 struct { 39 uint32_t ab1cr; 40 uint32_t ab2cr; 41 uint32_t ab3cr; 42 uint32_t ab4cr; 43 }; 44 }; 45 uint32_t sdtimr; 46 uint32_t ddrsr; 47 uint32_t ddrphycr; 48 uint32_t ddrphysr; 49 uint32_t totar; 50 uint32_t totactr; 51 uint32_t ddrphyid_rev; 52 uint32_t sdsretr; 53 uint32_t eirr; 54 uint32_t eimr; 55 uint32_t eimsr; 56 uint32_t eimcr; 57 uint32_t ioctrlr; 58 uint32_t iostatr; 59 uint32_t rsvd0; 60 uint32_t one_nand_cr; 61 uint32_t nandfcr; 62 uint32_t nandfsr; 63 uint32_t rsvd1[2]; 64 uint32_t nandfecc[4]; 65 uint32_t rsvd2[15]; 66 uint32_t nand4biteccload; 67 uint32_t nand4bitecc[4]; 68 uint32_t nanderradd1; 69 uint32_t nanderradd2; 70 uint32_t nanderrval1; 71 uint32_t nanderrval2; 72 }; 73 74 #define davinci_emif_regs \ 75 ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) 76 77 #define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) 78 #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) 79 #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) 80 #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) 81 #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) 82 #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) 83 #define DAVINCI_NANDFCR_CS2NAND (1 << 0) 84 85 /* Chip Select setup */ 86 #define DAVINCI_ABCR_STROBE_SELECT (1 << 31) 87 #define DAVINCI_ABCR_EXT_WAIT (1 << 30) 88 #define DAVINCI_ABCR_WSETUP(n) (n << 26) 89 #define DAVINCI_ABCR_WSTROBE(n) (n << 20) 90 #define DAVINCI_ABCR_WHOLD(n) (n << 17) 91 #define DAVINCI_ABCR_RSETUP(n) (n << 13) 92 #define DAVINCI_ABCR_RSTROBE(n) (n << 7) 93 #define DAVINCI_ABCR_RHOLD(n) (n << 4) 94 #define DAVINCI_ABCR_TA(n) (n << 2) 95 #define DAVINCI_ABCR_ASIZE_16BIT 1 96 #define DAVINCI_ABCR_ASIZE_8BIT 0 97 98 void davinci_nand_init(struct nand_chip *nand); 99 100 #endif 101
