1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Take linux kernel driver drivers/gpio/gpio-pca953x.c for reference. 4 * 5 * Copyright (C) 2016 Peng Fan <van.freenix (at) gmail.com> 6 * 7 */ 8 9 /* 10 * Note: 11 * The driver's compatible table is borrowed from Linux Kernel, 12 * but now max supported gpio pins is 24 and only PCA953X_TYPE 13 * is supported. PCA957X_TYPE is not supported now. 14 * Also the Polarity Inversion feature is not supported now. 15 * 16 * TODO: 17 * 1. Support PCA957X_TYPE 18 * 2. Support 24 gpio pins 19 * 3. Support Polarity Inversion 20 */ 21 22 #include <common.h> 23 #include <errno.h> 24 #include <dm.h> 25 #include <fdtdec.h> 26 #include <i2c.h> 27 #include <malloc.h> 28 #include <asm/gpio.h> 29 #include <asm/io.h> 30 #include <dt-bindings/gpio/gpio.h> 31 32 #define PCA953X_INPUT 0 33 #define PCA953X_OUTPUT 1 34 #define PCA953X_INVERT 2 35 #define PCA953X_DIRECTION 3 36 37 #define PCA_GPIO_MASK 0x00FF 38 #define PCA_INT 0x0100 39 #define PCA953X_TYPE 0x1000 40 #define PCA957X_TYPE 0x2000 41 #define PCA_TYPE_MASK 0xF000 42 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 43 44 enum { 45 PCA953X_DIRECTION_IN, 46 PCA953X_DIRECTION_OUT, 47 }; 48 49 #define MAX_BANK 5 50 #define BANK_SZ 8 51 52 /* 53 * struct pca953x_info - Data for pca953x 54 * 55 * @dev: udevice structure for the device 56 * @addr: i2c slave address 57 * @invert: Polarity inversion or not 58 * @gpio_count: the number of gpio pins that the device supports 59 * @chip_type: indicate the chip type,PCA953X or PCA957X 60 * @bank_count: the number of banks that the device supports 61 * @reg_output: array to hold the value of output registers 62 * @reg_direction: array to hold the value of direction registers 63 */ 64 struct pca953x_info { 65 struct udevice *dev; 66 int addr; 67 int invert; 68 int gpio_count; 69 int chip_type; 70 int bank_count; 71 u8 reg_output[MAX_BANK]; 72 u8 reg_direction[MAX_BANK]; 73 }; 74 75 static int pca953x_write_single(struct udevice *dev, int reg, u8 val, 76 int offset) 77 { 78 struct pca953x_info *info = dev_get_platdata(dev); 79 int bank_shift = fls((info->gpio_count - 1) / BANK_SZ); 80 int off = offset / BANK_SZ; 81 int ret = 0; 82 83 ret = dm_i2c_write(dev, (reg << bank_shift) + off, &val, 1); 84 if (ret) { 85 dev_err(dev, "%s error\n", __func__); 86 return ret; 87 } 88 89 return 0; 90 } 91 92 static int pca953x_read_single(struct udevice *dev, int reg, u8 *val, 93 int offset) 94 { 95 struct pca953x_info *info = dev_get_platdata(dev); 96 int bank_shift = fls((info->gpio_count - 1) / BANK_SZ); 97 int off = offset / BANK_SZ; 98 int ret; 99 u8 byte; 100 101 ret = dm_i2c_read(dev, (reg << bank_shift) + off, &byte, 1); 102 if (ret) { 103 dev_err(dev, "%s error\n", __func__); 104 return ret; 105 } 106 107 *val = byte; 108 109 return 0; 110 } 111 112 static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val) 113 { 114 struct pca953x_info *info = dev_get_platdata(dev); 115 int ret = 0; 116 117 if (info->gpio_count <= 8) { 118 ret = dm_i2c_read(dev, reg, val, 1); 119 } else if (info->gpio_count <= 16) { 120 ret = dm_i2c_read(dev, reg << 1, val, info->bank_count); 121 } else if (info->gpio_count == 40) { 122 /* Auto increment */ 123 ret = dm_i2c_read(dev, (reg << 3) | 0x80, val, 124 info->bank_count); 125 } else { 126 dev_err(dev, "Unsupported now\n"); 127 return -EINVAL; 128 } 129 130 return ret; 131 } 132 133 static int pca953x_is_output(struct udevice *dev, int offset) 134 { 135 struct pca953x_info *info = dev_get_platdata(dev); 136 137 int bank = offset / BANK_SZ; 138 int off = offset % BANK_SZ; 139 140 /*0: output; 1: input */ 141 return !(info->reg_direction[bank] & (1 << off)); 142 } 143 144 static int pca953x_get_value(struct udevice *dev, uint offset) 145 { 146 int ret; 147 u8 val = 0; 148 149 int off = offset % BANK_SZ; 150 151 ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset); 152 if (ret) 153 return ret; 154 155 return (val >> off) & 0x1; 156 } 157 158 static int pca953x_set_value(struct udevice *dev, uint offset, int value) 159 { 160 struct pca953x_info *info = dev_get_platdata(dev); 161 int bank = offset / BANK_SZ; 162 int off = offset % BANK_SZ; 163 u8 val; 164 int ret; 165 166 if (value) 167 val = info->reg_output[bank] | (1 << off); 168 else 169 val = info->reg_output[bank] & ~(1 << off); 170 171 ret = pca953x_write_single(dev, PCA953X_OUTPUT, val, offset); 172 if (ret) 173 return ret; 174 175 info->reg_output[bank] = val; 176 177 return 0; 178 } 179 180 static int pca953x_set_direction(struct udevice *dev, uint offset, int dir) 181 { 182 struct pca953x_info *info = dev_get_platdata(dev); 183 int bank = offset / BANK_SZ; 184 int off = offset % BANK_SZ; 185 u8 val; 186 int ret; 187 188 if (dir == PCA953X_DIRECTION_IN) 189 val = info->reg_direction[bank] | (1 << off); 190 else 191 val = info->reg_direction[bank] & ~(1 << off); 192 193 ret = pca953x_write_single(dev, PCA953X_DIRECTION, val, offset); 194 if (ret) 195 return ret; 196 197 info->reg_direction[bank] = val; 198 199 return 0; 200 } 201 202 static int pca953x_direction_input(struct udevice *dev, uint offset) 203 { 204 return pca953x_set_direction(dev, offset, PCA953X_DIRECTION_IN); 205 } 206 207 static int pca953x_direction_output(struct udevice *dev, uint offset, int value) 208 { 209 /* Configure output value. */ 210 pca953x_set_value(dev, offset, value); 211 212 /* Configure direction as output. */ 213 pca953x_set_direction(dev, offset, PCA953X_DIRECTION_OUT); 214 215 return 0; 216 } 217 218 static int pca953x_get_function(struct udevice *dev, uint offset) 219 { 220 if (pca953x_is_output(dev, offset)) 221 return GPIOF_OUTPUT; 222 else 223 return GPIOF_INPUT; 224 } 225 226 static int pca953x_xlate(struct udevice *dev, struct gpio_desc *desc, 227 struct ofnode_phandle_args *args) 228 { 229 desc->offset = args->args[0]; 230 desc->flags = args->args[1] & (GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0); 231 232 return 0; 233 } 234 235 static const struct dm_gpio_ops pca953x_ops = { 236 .direction_input = pca953x_direction_input, 237 .direction_output = pca953x_direction_output, 238 .get_value = pca953x_get_value, 239 .set_value = pca953x_set_value, 240 .get_function = pca953x_get_function, 241 .xlate = pca953x_xlate, 242 }; 243 244 static int pca953x_probe(struct udevice *dev) 245 { 246 struct pca953x_info *info = dev_get_platdata(dev); 247 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 248 char name[32], label[8], *str; 249 int addr; 250 ulong driver_data; 251 int ret; 252 int size; 253 const u8 *tmp; 254 255 addr = dev_read_addr(dev); 256 if (addr == 0) 257 return -ENODEV; 258 259 info->addr = addr; 260 261 driver_data = dev_get_driver_data(dev); 262 263 info->gpio_count = driver_data & PCA_GPIO_MASK; 264 if (info->gpio_count > MAX_BANK * BANK_SZ) { 265 dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ); 266 return -EINVAL; 267 } 268 269 info->chip_type = PCA_CHIP_TYPE(driver_data); 270 if (info->chip_type != PCA953X_TYPE) { 271 dev_err(dev, "Only support PCA953X chip type now.\n"); 272 return -EINVAL; 273 } 274 275 info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ); 276 277 ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output); 278 if (ret) { 279 dev_err(dev, "Error reading output register\n"); 280 return ret; 281 } 282 283 ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction); 284 if (ret) { 285 dev_err(dev, "Error reading direction register\n"); 286 return ret; 287 } 288 289 tmp = dev_read_prop(dev, "label", &size); 290 291 if (tmp) { 292 memcpy(label, tmp, sizeof(label) - 1); 293 label[sizeof(label) - 1] = '\0'; 294 snprintf(name, sizeof(name), "%s@%x_", label, info->addr); 295 } else { 296 snprintf(name, sizeof(name), "gpio@%x_", info->addr); 297 } 298 299 str = strdup(name); 300 if (!str) 301 return -ENOMEM; 302 uc_priv->bank_name = str; 303 uc_priv->gpio_count = info->gpio_count; 304 305 dev_dbg(dev, "%s is ready\n", str); 306 307 return 0; 308 } 309 310 #define OF_953X(__nrgpio, __int) (ulong)(__nrgpio | PCA953X_TYPE | __int) 311 #define OF_957X(__nrgpio, __int) (ulong)(__nrgpio | PCA957X_TYPE | __int) 312 313 static const struct udevice_id pca953x_ids[] = { 314 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 315 { .compatible = "nxp,pca9534", .data = OF_953X(8, PCA_INT), }, 316 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 317 { .compatible = "nxp,pca9536", .data = OF_953X(4, 0), }, 318 { .compatible = "nxp,pca9537", .data = OF_953X(4, PCA_INT), }, 319 { .compatible = "nxp,pca9538", .data = OF_953X(8, PCA_INT), }, 320 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 321 { .compatible = "nxp,pca9554", .data = OF_953X(8, PCA_INT), }, 322 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 323 { .compatible = "nxp,pca9556", .data = OF_953X(8, 0), }, 324 { .compatible = "nxp,pca9557", .data = OF_953X(8, 0), }, 325 { .compatible = "nxp,pca9574", .data = OF_957X(8, PCA_INT), }, 326 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 327 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 328 329 { .compatible = "maxim,max7310", .data = OF_953X(8, 0), }, 330 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 331 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 332 { .compatible = "maxim,max7315", .data = OF_953X(8, PCA_INT), }, 333 334 { .compatible = "ti,pca6107", .data = OF_953X(8, PCA_INT), }, 335 { .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), }, 336 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 337 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 338 339 { .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), }, 340 341 { .compatible = "exar,xra1202", .data = OF_953X(8, 0), }, 342 { } 343 }; 344 345 U_BOOT_DRIVER(pca953x) = { 346 .name = "pca953x", 347 .id = UCLASS_GPIO, 348 .ops = &pca953x_ops, 349 .probe = pca953x_probe, 350 .platdata_auto_alloc_size = sizeof(struct pca953x_info), 351 .of_match = pca953x_ids, 352 }; 353
