1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SH7780 PCI Controller (PCIC) for U-Boot. 4 * (C) Dustin McIntire (dustin (at) sensoria.com) 5 * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu (at) nigauri.org> 6 * (C) 2008 Yusuke Goda <goda.yusuke (at) renesas.com> 7 */ 8 9 #include <common.h> 10 11 #include <pci.h> 12 #include <asm/processor.h> 13 #include <asm/pci.h> 14 #include <asm/io.h> 15 16 #define SH7780_VENDOR_ID 0x1912 17 #define SH7780_DEVICE_ID 0x0002 18 #define SH7780_PCICR_PREFIX 0xA5000000 19 #define SH7780_PCICR_PFCS 0x00000800 20 #define SH7780_PCICR_FTO 0x00000400 21 #define SH7780_PCICR_PFE 0x00000200 22 #define SH7780_PCICR_TBS 0x00000100 23 #define SH7780_PCICR_ARBM 0x00000040 24 #define SH7780_PCICR_IOCS 0x00000004 25 #define SH7780_PCICR_PRST 0x00000002 26 #define SH7780_PCICR_CFIN 0x00000001 27 28 #define p4_in(addr) (*(vu_long *)addr) 29 #define p4_out(data, addr) (*(vu_long *)addr) = (data) 30 #define p4_inw(addr) (*(vu_short *)addr) 31 #define p4_outw(data, addr) (*(vu_short *)addr) = (data) 32 33 int pci_sh4_read_config_dword(struct pci_controller *hose, 34 pci_dev_t dev, int offset, u32 *value) 35 { 36 u32 par_data = 0x80000000 | dev; 37 38 p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR); 39 *value = p4_in(SH7780_PCIPDR); 40 41 return 0; 42 } 43 44 int pci_sh4_write_config_dword(struct pci_controller *hose, 45 pci_dev_t dev, int offset, u32 value) 46 { 47 u32 par_data = 0x80000000 | dev; 48 49 p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR); 50 p4_out(value, SH7780_PCIPDR); 51 return 0; 52 } 53 54 int pci_sh7780_init(struct pci_controller *hose) 55 { 56 p4_out(0x01, SH7780_PCIECR); 57 58 if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID 59 && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) { 60 printf("PCI: Unknown PCI host bridge.\n"); 61 return -1; 62 } 63 printf("PCI: SH7780 PCI host bridge found.\n"); 64 65 /* Toggle PCI reset pin */ 66 p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR); 67 udelay(100000); 68 p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR); 69 p4_outw(0x0047, SH7780_PCICMD); 70 71 p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0); 72 p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0); 73 p4_out(0x00000000, SH7780_PCILSR1); 74 p4_out(0, SH7780_PCILAR1); 75 p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0); 76 p4_out(0x00000000, SH7780_PCIMBAR1); 77 78 p4_out(0xFD000000, SH7780_PCIMBR0); 79 p4_out(0x00FC0000, SH7780_PCIMBMR0); 80 81 /* if use Operand Cache then enable PCICSCR Soonp bits. */ 82 p4_out(0x08000000, SH7780_PCICSAR0); 83 p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */ 84 85 p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM 86 | SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE), 87 SH7780_PCICR); 88 89 pci_sh4_init(hose); 90 return 0; 91 } 92
