1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Andreas Heppel <aheppel (at) sysgo.de> 5 * 6 * (C) Copyright 2002 7 * Wolfgang Denk, DENX Software Engineering, wd (at) denx.de. 8 */ 9 10 #ifndef _PCI_H 11 #define _PCI_H 12 13 #define PCI_CFG_SPACE_SIZE 256 14 #define PCI_CFG_SPACE_EXP_SIZE 4096 15 16 /* 17 * Under PCI, each device has 256 bytes of configuration address space, 18 * of which the first 64 bytes are standardized as follows: 19 */ 20 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 21 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 22 #define PCI_COMMAND 0x04 /* 16 bits */ 23 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 24 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 25 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 26 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 27 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 28 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 29 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 30 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 31 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 32 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 33 34 #define PCI_STATUS 0x06 /* 16 bits */ 35 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 36 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 37 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 38 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 39 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 40 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 41 #define PCI_STATUS_DEVSEL_FAST 0x000 42 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 43 #define PCI_STATUS_DEVSEL_SLOW 0x400 44 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 45 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 46 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 47 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 48 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 49 50 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 51 revision */ 52 #define PCI_REVISION_ID 0x08 /* Revision ID */ 53 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 54 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 55 #define PCI_CLASS_CODE 0x0b /* Device class code */ 56 #define PCI_CLASS_CODE_TOO_OLD 0x00 57 #define PCI_CLASS_CODE_STORAGE 0x01 58 #define PCI_CLASS_CODE_NETWORK 0x02 59 #define PCI_CLASS_CODE_DISPLAY 0x03 60 #define PCI_CLASS_CODE_MULTIMEDIA 0x04 61 #define PCI_CLASS_CODE_MEMORY 0x05 62 #define PCI_CLASS_CODE_BRIDGE 0x06 63 #define PCI_CLASS_CODE_COMM 0x07 64 #define PCI_CLASS_CODE_PERIPHERAL 0x08 65 #define PCI_CLASS_CODE_INPUT 0x09 66 #define PCI_CLASS_CODE_DOCKING 0x0A 67 #define PCI_CLASS_CODE_PROCESSOR 0x0B 68 #define PCI_CLASS_CODE_SERIAL 0x0C 69 #define PCI_CLASS_CODE_WIRELESS 0x0D 70 #define PCI_CLASS_CODE_I2O 0x0E 71 #define PCI_CLASS_CODE_SATELLITE 0x0F 72 #define PCI_CLASS_CODE_CRYPTO 0x10 73 #define PCI_CLASS_CODE_DATA 0x11 74 /* Base Class 0x12 - 0xFE is reserved */ 75 #define PCI_CLASS_CODE_OTHER 0xFF 76 77 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ 78 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 79 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 80 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 81 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 82 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 83 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 84 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 85 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 86 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 87 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 88 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 89 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 90 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 91 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 92 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 93 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 94 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 95 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 96 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 97 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 98 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 99 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 100 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 101 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 102 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 105 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 106 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 107 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 108 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 109 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 110 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 111 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 112 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 113 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 114 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 115 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 116 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 117 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 118 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A 119 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 120 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 121 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 122 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 123 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 124 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 125 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 126 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 127 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 128 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 134 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 135 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 136 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 137 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 138 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 139 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 140 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 141 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 142 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 143 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 144 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 145 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 146 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 147 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 148 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 149 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 150 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 151 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 152 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 153 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 154 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 155 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 156 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 157 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 158 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 159 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 160 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 161 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 162 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 163 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 164 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 165 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 166 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 167 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 168 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 169 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 170 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 171 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 172 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 173 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 174 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 175 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 176 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 177 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 178 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 179 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 180 181 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 182 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 183 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 184 #define PCI_HEADER_TYPE_NORMAL 0 185 #define PCI_HEADER_TYPE_BRIDGE 1 186 #define PCI_HEADER_TYPE_CARDBUS 2 187 188 #define PCI_BIST 0x0f /* 8 bits */ 189 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 190 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 191 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 192 193 /* 194 * Base addresses specify locations in memory or I/O space. 195 * Decoded size can be determined by writing a value of 196 * 0xffffffff to the register, and reading it back. Only 197 * 1 bits are decoded. 198 */ 199 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 200 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 201 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 202 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 203 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 204 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 205 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 206 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 207 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 208 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 209 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 210 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 211 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 212 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 213 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) 214 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) 215 /* bit 1 is reserved if address_space = 1 */ 216 217 /* Header type 0 (normal devices) */ 218 #define PCI_CARDBUS_CIS 0x28 219 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 220 #define PCI_SUBSYSTEM_ID 0x2e 221 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 222 #define PCI_ROM_ADDRESS_ENABLE 0x01 223 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL) 224 225 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 226 227 /* 0x35-0x3b are reserved */ 228 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 229 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 230 #define PCI_MIN_GNT 0x3e /* 8 bits */ 231 #define PCI_MAX_LAT 0x3f /* 8 bits */ 232 233 #define PCI_INTERRUPT_LINE_DISABLE 0xff 234 235 /* Header type 1 (PCI-to-PCI bridges) */ 236 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 237 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 238 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 239 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 240 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 241 #define PCI_IO_LIMIT 0x1d 242 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 243 #define PCI_IO_RANGE_TYPE_16 0x00 244 #define PCI_IO_RANGE_TYPE_32 0x01 245 #define PCI_IO_RANGE_MASK ~0x0f 246 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 247 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 248 #define PCI_MEMORY_LIMIT 0x22 249 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 250 #define PCI_MEMORY_RANGE_MASK ~0x0f 251 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 252 #define PCI_PREF_MEMORY_LIMIT 0x26 253 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 254 #define PCI_PREF_RANGE_TYPE_32 0x00 255 #define PCI_PREF_RANGE_TYPE_64 0x01 256 #define PCI_PREF_RANGE_MASK ~0x0f 257 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 258 #define PCI_PREF_LIMIT_UPPER32 0x2c 259 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 260 #define PCI_IO_LIMIT_UPPER16 0x32 261 /* 0x34 same as for htype 0 */ 262 /* 0x35-0x3b is reserved */ 263 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 264 /* 0x3c-0x3d are same as for htype 0 */ 265 #define PCI_BRIDGE_CONTROL 0x3e 266 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 267 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 268 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 269 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 270 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 271 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 272 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 273 274 /* From 440ep */ 275 #define PCI_ERREN 0x48 /* Error Enable */ 276 #define PCI_ERRSTS 0x49 /* Error Status */ 277 #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ 278 #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ 279 #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ 280 #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ 281 #define PCI_CAPID 0x58 /* Capability Identifier */ 282 #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ 283 #define PCI_PMC 0x5A /* Power Management Capabilities */ 284 #define PCI_PMCSR 0x5C /* Power Management Control Status */ 285 #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ 286 #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ 287 #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ 288 289 /* Header type 2 (CardBus bridges) */ 290 #define PCI_CB_CAPABILITY_LIST 0x14 291 /* 0x15 reserved */ 292 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 293 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 294 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 295 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 296 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 297 #define PCI_CB_MEMORY_BASE_0 0x1c 298 #define PCI_CB_MEMORY_LIMIT_0 0x20 299 #define PCI_CB_MEMORY_BASE_1 0x24 300 #define PCI_CB_MEMORY_LIMIT_1 0x28 301 #define PCI_CB_IO_BASE_0 0x2c 302 #define PCI_CB_IO_BASE_0_HI 0x2e 303 #define PCI_CB_IO_LIMIT_0 0x30 304 #define PCI_CB_IO_LIMIT_0_HI 0x32 305 #define PCI_CB_IO_BASE_1 0x34 306 #define PCI_CB_IO_BASE_1_HI 0x36 307 #define PCI_CB_IO_LIMIT_1 0x38 308 #define PCI_CB_IO_LIMIT_1_HI 0x3a 309 #define PCI_CB_IO_RANGE_MASK ~0x03 310 /* 0x3c-0x3d are same as for htype 0 */ 311 #define PCI_CB_BRIDGE_CONTROL 0x3e 312 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 313 #define PCI_CB_BRIDGE_CTL_SERR 0x02 314 #define PCI_CB_BRIDGE_CTL_ISA 0x04 315 #define PCI_CB_BRIDGE_CTL_VGA 0x08 316 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 317 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 318 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 319 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 320 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 321 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 322 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 323 #define PCI_CB_SUBSYSTEM_ID 0x42 324 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 325 /* 0x48-0x7f reserved */ 326 327 /* Capability lists */ 328 329 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 330 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 331 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 332 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 333 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 334 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 335 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 336 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 337 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 338 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 339 #define PCI_CAP_SIZEOF 4 340 341 /* Power Management Registers */ 342 343 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 344 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 345 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 346 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 347 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 348 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 349 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 350 #define PCI_PM_CTRL 4 /* PM control and status register */ 351 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 352 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 353 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 354 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 355 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 356 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 357 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 358 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 359 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 360 #define PCI_PM_SIZEOF 8 361 362 /* AGP registers */ 363 364 #define PCI_AGP_VERSION 2 /* BCD version number */ 365 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 366 #define PCI_AGP_STATUS 4 /* Status register */ 367 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 368 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 369 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 370 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 371 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 372 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 373 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 374 #define PCI_AGP_COMMAND 8 /* Control register */ 375 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 376 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 377 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 378 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 379 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 380 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 381 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ 382 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ 383 #define PCI_AGP_SIZEOF 12 384 385 /* PCI-X registers */ 386 387 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 388 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 389 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ 390 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ 391 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 392 393 394 /* Slot Identification */ 395 396 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 397 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 398 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 399 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 400 401 /* Message Signalled Interrupts registers */ 402 403 #define PCI_MSI_FLAGS 2 /* Various flags */ 404 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 405 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 406 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 407 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 408 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 409 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 410 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 411 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 412 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 413 414 #define PCI_MAX_PCI_DEVICES 32 415 #define PCI_MAX_PCI_FUNCTIONS 8 416 417 #define PCI_FIND_CAP_TTL 0x48 418 #define CAP_START_POS 0x40 419 420 /* Extended Capabilities (PCI-X 2.0 and Express) */ 421 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 422 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 423 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 424 425 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 426 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 427 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 428 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 429 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 430 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 431 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 432 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 433 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 434 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 435 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 436 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 437 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 438 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 439 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 440 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 441 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 442 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 443 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 444 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 445 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 446 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 447 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 448 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 449 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 450 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 451 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 452 453 /* Include the ID list */ 454 455 #include <pci_ids.h> 456 457 #ifndef __ASSEMBLY__ 458 459 #ifdef CONFIG_SYS_PCI_64BIT 460 typedef u64 pci_addr_t; 461 typedef u64 pci_size_t; 462 #else 463 typedef u32 pci_addr_t; 464 typedef u32 pci_size_t; 465 #endif 466 467 struct pci_region { 468 pci_addr_t bus_start; /* Start on the bus */ 469 phys_addr_t phys_start; /* Start in physical address space */ 470 pci_size_t size; /* Size */ 471 unsigned long flags; /* Resource flags */ 472 473 pci_addr_t bus_lower; 474 }; 475 476 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ 477 #define PCI_REGION_IO 0x00000001 /* PCI IO space */ 478 #define PCI_REGION_TYPE 0x00000001 479 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ 480 481 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ 482 #define PCI_REGION_RO 0x00000200 /* Read-only memory */ 483 484 static inline void pci_set_region(struct pci_region *reg, 485 pci_addr_t bus_start, 486 phys_addr_t phys_start, 487 pci_size_t size, 488 unsigned long flags) { 489 reg->bus_start = bus_start; 490 reg->phys_start = phys_start; 491 reg->size = size; 492 reg->flags = flags; 493 } 494 495 typedef int pci_dev_t; 496 497 #define PCI_BUS(d) (((d) >> 16) & 0xff) 498 #define PCI_DEV(d) (((d) >> 11) & 0x1f) 499 #define PCI_FUNC(d) (((d) >> 8) & 0x7) 500 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8) 501 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) 502 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) 503 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) 504 #define PCI_VENDEV(v, d) (((v) << 16) | (d)) 505 #define PCI_ANY_ID (~0) 506 507 struct pci_device_id { 508 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 509 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ 510 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ 511 unsigned long driver_data; /* Data private to the driver */ 512 }; 513 514 struct pci_controller; 515 516 struct pci_config_table { 517 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 518 unsigned int class; /* Class ID, or PCI_ANY_ID */ 519 unsigned int bus; /* Bus number, or PCI_ANY_ID */ 520 unsigned int dev; /* Device number, or PCI_ANY_ID */ 521 unsigned int func; /* Function number, or PCI_ANY_ID */ 522 523 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 524 struct pci_config_table *); 525 unsigned long priv[3]; 526 }; 527 528 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 529 struct pci_config_table *); 530 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 531 struct pci_config_table *); 532 533 #define MAX_PCI_REGIONS 7 534 535 #define INDIRECT_TYPE_NO_PCIE_LINK 1 536 537 /* 538 * Structure of a PCI controller (host bridge) 539 * 540 * With driver model this is dev_get_uclass_priv(bus) 541 */ 542 struct pci_controller { 543 #ifdef CONFIG_DM_PCI 544 struct udevice *bus; 545 struct udevice *ctlr; 546 #else 547 struct pci_controller *next; 548 #endif 549 550 int first_busno; 551 int last_busno; 552 553 volatile unsigned int *cfg_addr; 554 volatile unsigned char *cfg_data; 555 556 int indirect_type; 557 558 /* 559 * TODO(sjg (at) chromium.org): With driver model we use struct 560 * pci_controller for both the controller and any bridge devices 561 * attached to it. But there is only one region list and it is in the 562 * top-level controller. 563 * 564 * This could be changed so that struct pci_controller is only used 565 * for PCI controllers and a separate UCLASS (or perhaps 566 * UCLASS_PCI_GENERIC) is used for bridges. 567 */ 568 struct pci_region regions[MAX_PCI_REGIONS]; 569 int region_count; 570 571 struct pci_config_table *config_table; 572 573 void (*fixup_irq)(struct pci_controller *, pci_dev_t); 574 #ifndef CONFIG_DM_PCI 575 /* Low-level architecture-dependent routines */ 576 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); 577 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); 578 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); 579 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); 580 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); 581 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); 582 #endif 583 584 /* Used by auto config */ 585 struct pci_region *pci_mem, *pci_io, *pci_prefetch; 586 587 #ifndef CONFIG_DM_PCI 588 int current_busno; 589 590 void *priv_data; 591 #endif 592 }; 593 594 #ifndef CONFIG_DM_PCI 595 static inline void pci_set_ops(struct pci_controller *hose, 596 int (*read_byte)(struct pci_controller*, 597 pci_dev_t, int where, u8 *), 598 int (*read_word)(struct pci_controller*, 599 pci_dev_t, int where, u16 *), 600 int (*read_dword)(struct pci_controller*, 601 pci_dev_t, int where, u32 *), 602 int (*write_byte)(struct pci_controller*, 603 pci_dev_t, int where, u8), 604 int (*write_word)(struct pci_controller*, 605 pci_dev_t, int where, u16), 606 int (*write_dword)(struct pci_controller*, 607 pci_dev_t, int where, u32)) { 608 hose->read_byte = read_byte; 609 hose->read_word = read_word; 610 hose->read_dword = read_dword; 611 hose->write_byte = write_byte; 612 hose->write_word = write_word; 613 hose->write_dword = write_dword; 614 } 615 #endif 616 617 #ifdef CONFIG_PCI_INDIRECT_BRIDGE 618 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); 619 #endif 620 621 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 622 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 623 pci_addr_t addr, unsigned long flags); 624 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 625 phys_addr_t addr, unsigned long flags); 626 627 #define pci_phys_to_bus(dev, addr, flags) \ 628 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 629 #define pci_bus_to_phys(dev, addr, flags) \ 630 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 631 632 #define pci_virt_to_bus(dev, addr, flags) \ 633 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ 634 (virt_to_phys(addr)), (flags)) 635 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 636 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ 637 (addr), (flags)), \ 638 (len), (map_flags)) 639 640 #define pci_phys_to_mem(dev, addr) \ 641 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 642 #define pci_mem_to_phys(dev, addr) \ 643 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 644 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 645 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 646 647 #define pci_virt_to_mem(dev, addr) \ 648 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 649 #define pci_mem_to_virt(dev, addr, len, map_flags) \ 650 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 651 #define pci_virt_to_io(dev, addr) \ 652 pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 653 #define pci_io_to_virt(dev, addr, len, map_flags) \ 654 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 655 656 /* For driver model these are defined in macros in pci_compat.c */ 657 extern int pci_hose_read_config_byte(struct pci_controller *hose, 658 pci_dev_t dev, int where, u8 *val); 659 extern int pci_hose_read_config_word(struct pci_controller *hose, 660 pci_dev_t dev, int where, u16 *val); 661 extern int pci_hose_read_config_dword(struct pci_controller *hose, 662 pci_dev_t dev, int where, u32 *val); 663 extern int pci_hose_write_config_byte(struct pci_controller *hose, 664 pci_dev_t dev, int where, u8 val); 665 extern int pci_hose_write_config_word(struct pci_controller *hose, 666 pci_dev_t dev, int where, u16 val); 667 extern int pci_hose_write_config_dword(struct pci_controller *hose, 668 pci_dev_t dev, int where, u32 val); 669 #endif 670 671 #ifndef CONFIG_DM_PCI 672 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); 673 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); 674 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); 675 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); 676 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); 677 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); 678 #endif 679 680 void pciauto_region_init(struct pci_region *res); 681 void pciauto_region_align(struct pci_region *res, pci_size_t size); 682 void pciauto_config_init(struct pci_controller *hose); 683 684 /** 685 * pciauto_region_allocate() - Allocate resources from a PCI resource region 686 * 687 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is 688 * false, the result will be guaranteed to fit in 32 bits. 689 * 690 * @res: PCI region to allocate from 691 * @size: Amount of bytes to allocate 692 * @bar: Returns the PCI bus address of the allocated resource 693 * @supports_64bit: Whether to allow allocations above the 32-bit boundary 694 * @return 0 if successful, -1 on failure 695 */ 696 int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 697 pci_addr_t *bar, bool supports_64bit); 698 699 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 700 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, 701 pci_dev_t dev, int where, u8 *val); 702 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, 703 pci_dev_t dev, int where, u16 *val); 704 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, 705 pci_dev_t dev, int where, u8 val); 706 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, 707 pci_dev_t dev, int where, u16 val); 708 709 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); 710 extern void pci_register_hose(struct pci_controller* hose); 711 extern struct pci_controller* pci_bus_to_hose(int bus); 712 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); 713 extern struct pci_controller *pci_get_hose_head(void); 714 715 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); 716 extern int pci_hose_scan(struct pci_controller *hose); 717 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); 718 719 extern void pciauto_setup_device(struct pci_controller *hose, 720 pci_dev_t dev, int bars_num, 721 struct pci_region *mem, 722 struct pci_region *prefetch, 723 struct pci_region *io); 724 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, 725 pci_dev_t dev, int sub_bus); 726 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, 727 pci_dev_t dev, int sub_bus); 728 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 729 730 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); 731 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); 732 pci_dev_t pci_find_class(unsigned int find_class, int index); 733 734 extern int pci_hose_config_device(struct pci_controller *hose, 735 pci_dev_t dev, 736 unsigned long io, 737 pci_addr_t mem, 738 unsigned long command); 739 740 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 741 int cap); 742 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 743 u8 hdr_type); 744 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, 745 int cap); 746 747 int pci_find_next_ext_capability(struct pci_controller *hose, 748 pci_dev_t dev, int start, int cap); 749 int pci_hose_find_ext_capability(struct pci_controller *hose, 750 pci_dev_t dev, int cap); 751 752 #ifdef CONFIG_PCI_FIXUP_DEV 753 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 754 unsigned short vendor, 755 unsigned short device, 756 unsigned short class); 757 #endif 758 #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ 759 760 const char * pci_class_str(u8 class); 761 int pci_last_busno(void); 762 763 #ifdef CONFIG_MPC85xx 764 extern void pci_mpc85xx_init (struct pci_controller *hose); 765 #endif 766 767 #ifdef CONFIG_PCIE_IMX 768 extern void imx_pcie_remove(void); 769 #endif 770 771 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 772 /** 773 * pci_write_bar32() - Write the address of a BAR including control bits 774 * 775 * This writes a raw address (with control bits) to a bar. This can be used 776 * with devices which require hard-coded addresses, not part of the normal 777 * PCI enumeration process. 778 * 779 * @hose: PCI hose to use 780 * @dev: PCI device to update 781 * @barnum: BAR number (0-5) 782 * @addr: BAR address with control bits 783 */ 784 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, 785 u32 addr); 786 787 /** 788 * pci_read_bar32() - read the address of a bar 789 * 790 * @hose: PCI hose to use 791 * @dev: PCI device to inspect 792 * @barnum: BAR number (0-5) 793 * @return address of the bar, masking out any control bits 794 * */ 795 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); 796 797 /** 798 * pci_hose_find_devices() - Find devices by vendor/device ID 799 * 800 * @hose: PCI hose to search 801 * @busnum: Bus number to search 802 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 803 * @indexp: Pointer to device index to find. To find the first matching 804 * device, pass 0; to find the second, pass 1, etc. This 805 * parameter is decremented for each non-matching device so 806 * can be called repeatedly. 807 */ 808 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, 809 struct pci_device_id *ids, int *indexp); 810 #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ 811 812 /* Access sizes for PCI reads and writes */ 813 enum pci_size_t { 814 PCI_SIZE_8, 815 PCI_SIZE_16, 816 PCI_SIZE_32, 817 }; 818 819 struct udevice; 820 821 #ifdef CONFIG_DM_PCI 822 /** 823 * struct pci_child_platdata - information stored about each PCI device 824 * 825 * Every device on a PCI bus has this per-child data. 826 * 827 * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a 828 * PCI bus (i.e. UCLASS_PCI) 829 * 830 * @devfn: Encoded device and function index - see PCI_DEVFN() 831 * @vendor: PCI vendor ID (see pci_ids.h) 832 * @device: PCI device ID (see pci_ids.h) 833 * @class: PCI class, 3 bytes: (base, sub, prog-if) 834 */ 835 struct pci_child_platdata { 836 int devfn; 837 unsigned short vendor; 838 unsigned short device; 839 unsigned int class; 840 }; 841 842 /* PCI bus operations */ 843 struct dm_pci_ops { 844 /** 845 * read_config() - Read a PCI configuration value 846 * 847 * PCI buses must support reading and writing configuration values 848 * so that the bus can be scanned and its devices configured. 849 * 850 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always. 851 * If bridges exist it is possible to use the top-level bus to 852 * access a sub-bus. In that case @bus will be the top-level bus 853 * and PCI_BUS(bdf) will be a different (higher) value 854 * 855 * @bus: Bus to read from 856 * @bdf: Bus, device and function to read 857 * @offset: Byte offset within the device's configuration space 858 * @valuep: Place to put the returned value 859 * @size: Access size 860 * @return 0 if OK, -ve on error 861 */ 862 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 863 ulong *valuep, enum pci_size_t size); 864 /** 865 * write_config() - Write a PCI configuration value 866 * 867 * @bus: Bus to write to 868 * @bdf: Bus, device and function to write 869 * @offset: Byte offset within the device's configuration space 870 * @value: Value to write 871 * @size: Access size 872 * @return 0 if OK, -ve on error 873 */ 874 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 875 ulong value, enum pci_size_t size); 876 }; 877 878 /* Get access to a PCI bus' operations */ 879 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops) 880 881 /** 882 * dm_pci_get_bdf() - Get the BDF value for a device 883 * 884 * @dev: Device to check 885 * @return bus/device/function value (see PCI_BDF()) 886 */ 887 pci_dev_t dm_pci_get_bdf(struct udevice *dev); 888 889 /** 890 * pci_bind_bus_devices() - scan a PCI bus and bind devices 891 * 892 * Scan a PCI bus looking for devices. Bind each one that is found. If 893 * devices are already bound that match the scanned devices, just update the 894 * child data so that the device can be used correctly (this happens when 895 * the device tree describes devices we expect to see on the bus). 896 * 897 * Devices that are bound in this way will use a generic PCI driver which 898 * does nothing. The device can still be accessed but will not provide any 899 * driver interface. 900 * 901 * @bus: Bus containing devices to bind 902 * @return 0 if OK, -ve on error 903 */ 904 int pci_bind_bus_devices(struct udevice *bus); 905 906 /** 907 * pci_auto_config_devices() - configure bus devices ready for use 908 * 909 * This works through all devices on a bus by scanning the driver model 910 * data structures (normally these have been set up by pci_bind_bus_devices() 911 * earlier). 912 * 913 * Space is allocated for each PCI base address register (BAR) so that the 914 * devices are mapped into memory and I/O space ready for use. 915 * 916 * @bus: Bus containing devices to bind 917 * @return 0 if OK, -ve on error 918 */ 919 int pci_auto_config_devices(struct udevice *bus); 920 921 /** 922 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address 923 * 924 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 925 * @devp: Returns the device for this address, if found 926 * @return 0 if OK, -ENODEV if not found 927 */ 928 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); 929 930 /** 931 * pci_bus_find_devfn() - Find a device on a bus 932 * 933 * @find_devfn: PCI device address (device and function only) 934 * @devp: Returns the device for this address, if found 935 * @return 0 if OK, -ENODEV if not found 936 */ 937 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, 938 struct udevice **devp); 939 940 /** 941 * pci_find_first_device() - return the first available PCI device 942 * 943 * This function and pci_find_first_device() allow iteration through all 944 * available PCI devices on all buses. Assuming there are any, this will 945 * return the first one. 946 * 947 * @devp: Set to the first available device, or NULL if no more are left 948 * or we got an error 949 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 950 */ 951 int pci_find_first_device(struct udevice **devp); 952 953 /** 954 * pci_find_next_device() - return the next available PCI device 955 * 956 * Finds the next available PCI device after the one supplied, or sets @devp 957 * to NULL if there are no more. 958 * 959 * @devp: On entry, the last device returned. Set to the next available 960 * device, or NULL if no more are left or we got an error 961 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 962 */ 963 int pci_find_next_device(struct udevice **devp); 964 965 /** 966 * pci_get_ff() - Returns a mask for the given access size 967 * 968 * @size: Access size 969 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for 970 * PCI_SIZE_32 971 */ 972 int pci_get_ff(enum pci_size_t size); 973 974 /** 975 * pci_bus_find_devices () - Find devices on a bus 976 * 977 * @bus: Bus to search 978 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 979 * @indexp: Pointer to device index to find. To find the first matching 980 * device, pass 0; to find the second, pass 1, etc. This 981 * parameter is decremented for each non-matching device so 982 * can be called repeatedly. 983 * @devp: Returns matching device if found 984 * @return 0 if found, -ENODEV if not 985 */ 986 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, 987 int *indexp, struct udevice **devp); 988 989 /** 990 * pci_find_device_id() - Find a device on any bus 991 * 992 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 993 * @index: Index number of device to find, 0 for the first match, 1 for 994 * the second, etc. 995 * @devp: Returns matching device if found 996 * @return 0 if found, -ENODEV if not 997 */ 998 int pci_find_device_id(struct pci_device_id *ids, int index, 999 struct udevice **devp); 1000 1001 /** 1002 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices 1003 * 1004 * This probes the given bus which causes it to be scanned for devices. The 1005 * devices will be bound but not probed. 1006 * 1007 * @hose specifies the PCI hose that will be used for the scan. This is 1008 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is 1009 * in @bdf, and is a subordinate bus reachable from @hose. 1010 * 1011 * @hose: PCI hose to scan 1012 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) 1013 * @return 0 if OK, -ve on error 1014 */ 1015 int dm_pci_hose_probe_bus(struct udevice *bus); 1016 1017 /** 1018 * pci_bus_read_config() - Read a configuration value from a device 1019 * 1020 * TODO(sjg (at) chromium.org): We should be able to pass just a device and have 1021 * it do the right thing. It would be good to have that function also. 1022 * 1023 * @bus: Bus to read from 1024 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1025 * @offset: Register offset to read 1026 * @valuep: Place to put the returned value 1027 * @size: Access size 1028 * @return 0 if OK, -ve on error 1029 */ 1030 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, 1031 unsigned long *valuep, enum pci_size_t size); 1032 1033 /** 1034 * pci_bus_write_config() - Write a configuration value to a device 1035 * 1036 * @bus: Bus to write from 1037 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1038 * @offset: Register offset to write 1039 * @value: Value to write 1040 * @size: Access size 1041 * @return 0 if OK, -ve on error 1042 */ 1043 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 1044 unsigned long value, enum pci_size_t size); 1045 1046 /** 1047 * pci_bus_clrset_config32() - Update a configuration value for a device 1048 * 1049 * The register at @offset is updated to (oldvalue & ~clr) | set. 1050 * 1051 * @bus: Bus to access 1052 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1053 * @offset: Register offset to update 1054 * @clr: Bits to clear 1055 * @set: Bits to set 1056 * @return 0 if OK, -ve on error 1057 */ 1058 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, 1059 u32 clr, u32 set); 1060 1061 /** 1062 * Driver model PCI config access functions. Use these in preference to others 1063 * when you have a valid device 1064 */ 1065 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, 1066 enum pci_size_t size); 1067 1068 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep); 1069 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep); 1070 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep); 1071 1072 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, 1073 enum pci_size_t size); 1074 1075 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value); 1076 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value); 1077 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); 1078 1079 /** 1080 * These permit convenient read/modify/write on PCI configuration. The 1081 * register is updated to (oldvalue & ~clr) | set. 1082 */ 1083 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set); 1084 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set); 1085 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set); 1086 1087 /* 1088 * The following functions provide access to the above without needing the 1089 * size parameter. We are trying to encourage the use of the 8/16/32-style 1090 * functions, rather than byte/word/dword. But both are supported. 1091 */ 1092 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); 1093 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); 1094 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); 1095 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); 1096 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); 1097 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); 1098 1099 /** 1100 * pci_generic_mmap_write_config() - Generic helper for writing to 1101 * memory-mapped PCI configuration space. 1102 * @bus: Pointer to the PCI bus 1103 * @addr_f: Callback for calculating the config space address 1104 * @bdf: Identifies the PCI device to access 1105 * @offset: The offset into the device's configuration space 1106 * @value: The value to write 1107 * @size: Indicates the size of access to perform 1108 * 1109 * Write the value @value of size @size from offset @offset within the 1110 * configuration space of the device identified by the bus, device & function 1111 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is 1112 * responsible for calculating the CPU address of the respective configuration 1113 * space offset. 1114 * 1115 * Return: 0 on success, else -EINVAL 1116 */ 1117 int pci_generic_mmap_write_config( 1118 struct udevice *bus, 1119 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), 1120 pci_dev_t bdf, 1121 uint offset, 1122 ulong value, 1123 enum pci_size_t size); 1124 1125 /** 1126 * pci_generic_mmap_read_config() - Generic helper for reading from 1127 * memory-mapped PCI configuration space. 1128 * @bus: Pointer to the PCI bus 1129 * @addr_f: Callback for calculating the config space address 1130 * @bdf: Identifies the PCI device to access 1131 * @offset: The offset into the device's configuration space 1132 * @valuep: A pointer at which to store the read value 1133 * @size: Indicates the size of access to perform 1134 * 1135 * Read a value of size @size from offset @offset within the configuration 1136 * space of the device identified by the bus, device & function numbers in @bdf 1137 * on the PCI bus @bus. The callback function @addr_f is responsible for 1138 * calculating the CPU address of the respective configuration space offset. 1139 * 1140 * Return: 0 on success, else -EINVAL 1141 */ 1142 int pci_generic_mmap_read_config( 1143 struct udevice *bus, 1144 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), 1145 pci_dev_t bdf, 1146 uint offset, 1147 ulong *valuep, 1148 enum pci_size_t size); 1149 1150 #ifdef CONFIG_DM_PCI_COMPAT 1151 /* Compatibility with old naming */ 1152 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, 1153 u32 value) 1154 { 1155 return pci_write_config32(pcidev, offset, value); 1156 } 1157 1158 /* Compatibility with old naming */ 1159 static inline int pci_write_config_word(pci_dev_t pcidev, int offset, 1160 u16 value) 1161 { 1162 return pci_write_config16(pcidev, offset, value); 1163 } 1164 1165 /* Compatibility with old naming */ 1166 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, 1167 u8 value) 1168 { 1169 return pci_write_config8(pcidev, offset, value); 1170 } 1171 1172 /* Compatibility with old naming */ 1173 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, 1174 u32 *valuep) 1175 { 1176 return pci_read_config32(pcidev, offset, valuep); 1177 } 1178 1179 /* Compatibility with old naming */ 1180 static inline int pci_read_config_word(pci_dev_t pcidev, int offset, 1181 u16 *valuep) 1182 { 1183 return pci_read_config16(pcidev, offset, valuep); 1184 } 1185 1186 /* Compatibility with old naming */ 1187 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, 1188 u8 *valuep) 1189 { 1190 return pci_read_config8(pcidev, offset, valuep); 1191 } 1192 #endif /* CONFIG_DM_PCI_COMPAT */ 1193 1194 /** 1195 * dm_pciauto_config_device() - configure a device ready for use 1196 * 1197 * Space is allocated for each PCI base address register (BAR) so that the 1198 * devices are mapped into memory and I/O space ready for use. 1199 * 1200 * @dev: Device to configure 1201 * @return 0 if OK, -ve on error 1202 */ 1203 int dm_pciauto_config_device(struct udevice *dev); 1204 1205 /** 1206 * pci_conv_32_to_size() - convert a 32-bit read value to the given size 1207 * 1208 * Some PCI buses must always perform 32-bit reads. The data must then be 1209 * shifted and masked to reflect the required access size and offset. This 1210 * function performs this transformation. 1211 * 1212 * @value: Value to transform (32-bit value read from @offset & ~3) 1213 * @offset: Register offset that was read 1214 * @size: Required size of the result 1215 * @return the value that would have been obtained if the read had been 1216 * performed at the given offset with the correct size 1217 */ 1218 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); 1219 1220 /** 1221 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write 1222 * 1223 * Some PCI buses must always perform 32-bit writes. To emulate a smaller 1224 * write the old 32-bit data must be read, updated with the required new data 1225 * and written back as a 32-bit value. This function performs the 1226 * transformation from the old value to the new value. 1227 * 1228 * @value: Value to transform (32-bit value read from @offset & ~3) 1229 * @offset: Register offset that should be written 1230 * @size: Required size of the write 1231 * @return the value that should be written as a 32-bit access to @offset & ~3. 1232 */ 1233 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, 1234 enum pci_size_t size); 1235 1236 /** 1237 * pci_get_controller() - obtain the controller to use for a bus 1238 * 1239 * @dev: Device to check 1240 * @return pointer to the controller device for this bus 1241 */ 1242 struct udevice *pci_get_controller(struct udevice *dev); 1243 1244 /** 1245 * pci_get_regions() - obtain pointers to all the region types 1246 * 1247 * @dev: Device to check 1248 * @iop: Returns a pointer to the I/O region, or NULL if none 1249 * @memp: Returns a pointer to the memory region, or NULL if none 1250 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none 1251 * @return the number of non-NULL regions returned, normally 3 1252 */ 1253 int pci_get_regions(struct udevice *dev, struct pci_region **iop, 1254 struct pci_region **memp, struct pci_region **prefp); 1255 1256 /** 1257 * dm_pci_write_bar32() - Write the address of a BAR 1258 * 1259 * This writes a raw address to a bar 1260 * 1261 * @dev: PCI device to update 1262 * @barnum: BAR number (0-5) 1263 * @addr: BAR address 1264 */ 1265 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr); 1266 1267 /** 1268 * dm_pci_read_bar32() - read a base address register from a device 1269 * 1270 * @dev: Device to check 1271 * @barnum: Bar number to read (numbered from 0) 1272 * @return: value of BAR 1273 */ 1274 u32 dm_pci_read_bar32(struct udevice *dev, int barnum); 1275 1276 /** 1277 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address 1278 * 1279 * @dev: Device containing the PCI address 1280 * @addr: PCI address to convert 1281 * @flags: Flags for the region type (PCI_REGION_...) 1282 * @return physical address corresponding to that PCI bus address 1283 */ 1284 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, 1285 unsigned long flags); 1286 1287 /** 1288 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address 1289 * 1290 * @dev: Device containing the bus address 1291 * @addr: Physical address to convert 1292 * @flags: Flags for the region type (PCI_REGION_...) 1293 * @return PCI bus address corresponding to that physical address 1294 */ 1295 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, 1296 unsigned long flags); 1297 1298 /** 1299 * dm_pci_map_bar() - get a virtual address associated with a BAR region 1300 * 1301 * Looks up a base address register and finds the physical memory address 1302 * that corresponds to it 1303 * 1304 * @dev: Device to check 1305 * @bar: Bar number to read (numbered from 0) 1306 * @flags: Flags for the region type (PCI_REGION_...) 1307 * @return: pointer to the virtual address to use 1308 */ 1309 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); 1310 1311 #define dm_pci_virt_to_bus(dev, addr, flags) \ 1312 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) 1313 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 1314 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \ 1315 (len), (map_flags)) 1316 1317 #define dm_pci_phys_to_mem(dev, addr) \ 1318 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 1319 #define dm_pci_mem_to_phys(dev, addr) \ 1320 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 1321 #define dm_pci_phys_to_io(dev, addr) \ 1322 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 1323 #define dm_pci_io_to_phys(dev, addr) \ 1324 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 1325 1326 #define dm_pci_virt_to_mem(dev, addr) \ 1327 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 1328 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \ 1329 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 1330 #define dm_pci_virt_to_io(dev, addr) \ 1331 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 1332 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \ 1333 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 1334 1335 /** 1336 * dm_pci_find_device() - find a device by vendor/device ID 1337 * 1338 * @vendor: Vendor ID 1339 * @device: Device ID 1340 * @index: 0 to find the first match, 1 for second, etc. 1341 * @devp: Returns pointer to the device, if found 1342 * @return 0 if found, -ve on error 1343 */ 1344 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, 1345 struct udevice **devp); 1346 1347 /** 1348 * dm_pci_find_class() - find a device by class 1349 * 1350 * @find_class: 3-byte (24-bit) class value to find 1351 * @index: 0 to find the first match, 1 for second, etc. 1352 * @devp: Returns pointer to the device, if found 1353 * @return 0 if found, -ve on error 1354 */ 1355 int dm_pci_find_class(uint find_class, int index, struct udevice **devp); 1356 1357 /** 1358 * struct dm_pci_emul_ops - PCI device emulator operations 1359 */ 1360 struct dm_pci_emul_ops { 1361 /** 1362 * get_devfn(): Check which device and function this emulators 1363 * 1364 * @dev: device to check 1365 * @return the device and function this emulates, or -ve on error 1366 */ 1367 int (*get_devfn)(struct udevice *dev); 1368 /** 1369 * read_config() - Read a PCI configuration value 1370 * 1371 * @dev: Emulated device to read from 1372 * @offset: Byte offset within the device's configuration space 1373 * @valuep: Place to put the returned value 1374 * @size: Access size 1375 * @return 0 if OK, -ve on error 1376 */ 1377 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep, 1378 enum pci_size_t size); 1379 /** 1380 * write_config() - Write a PCI configuration value 1381 * 1382 * @dev: Emulated device to write to 1383 * @offset: Byte offset within the device's configuration space 1384 * @value: Value to write 1385 * @size: Access size 1386 * @return 0 if OK, -ve on error 1387 */ 1388 int (*write_config)(struct udevice *dev, uint offset, ulong value, 1389 enum pci_size_t size); 1390 /** 1391 * read_io() - Read a PCI I/O value 1392 * 1393 * @dev: Emulated device to read from 1394 * @addr: I/O address to read 1395 * @valuep: Place to put the returned value 1396 * @size: Access size 1397 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1398 * other -ve value on error 1399 */ 1400 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep, 1401 enum pci_size_t size); 1402 /** 1403 * write_io() - Write a PCI I/O value 1404 * 1405 * @dev: Emulated device to write from 1406 * @addr: I/O address to write 1407 * @value: Value to write 1408 * @size: Access size 1409 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1410 * other -ve value on error 1411 */ 1412 int (*write_io)(struct udevice *dev, unsigned int addr, 1413 ulong value, enum pci_size_t size); 1414 /** 1415 * map_physmem() - Map a device into sandbox memory 1416 * 1417 * @dev: Emulated device to map 1418 * @addr: Memory address, normally corresponding to a PCI BAR. 1419 * The device should have been configured to have a BAR 1420 * at this address. 1421 * @lenp: On entry, the size of the area to map, On exit it is 1422 * updated to the size actually mapped, which may be less 1423 * if the device has less space 1424 * @ptrp: Returns a pointer to the mapped address. The device's 1425 * space can be accessed as @lenp bytes starting here 1426 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1427 * other -ve value on error 1428 */ 1429 int (*map_physmem)(struct udevice *dev, phys_addr_t addr, 1430 unsigned long *lenp, void **ptrp); 1431 /** 1432 * unmap_physmem() - undo a memory mapping 1433 * 1434 * This must be called after map_physmem() to undo the mapping. 1435 * Some devices can use this to check what has been written into 1436 * their mapped memory and perform an operations they require on it. 1437 * In this way, map/unmap can be used as a sort of handshake between 1438 * the emulated device and its users. 1439 * 1440 * @dev: Emuated device to unmap 1441 * @vaddr: Mapped memory address, as passed to map_physmem() 1442 * @len: Size of area mapped, as returned by map_physmem() 1443 * @return 0 if OK, -ve on error 1444 */ 1445 int (*unmap_physmem)(struct udevice *dev, const void *vaddr, 1446 unsigned long len); 1447 }; 1448 1449 /* Get access to a PCI device emulator's operations */ 1450 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops) 1451 1452 /** 1453 * sandbox_pci_get_emul() - Get the emulation device for a PCI device 1454 * 1455 * Searches for a suitable emulator for the given PCI bus device 1456 * 1457 * @bus: PCI bus to search 1458 * @find_devfn: PCI device and function address (PCI_DEVFN()) 1459 * @emulp: Returns emulated device if found 1460 * @return 0 if found, -ENODEV if not found 1461 */ 1462 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, 1463 struct udevice **emulp); 1464 1465 #endif /* CONFIG_DM_PCI */ 1466 1467 /** 1468 * PCI_DEVICE - macro used to describe a specific pci device 1469 * @vend: the 16 bit PCI Vendor ID 1470 * @dev: the 16 bit PCI Device ID 1471 * 1472 * This macro is used to create a struct pci_device_id that matches a 1473 * specific device. The subvendor and subdevice fields will be set to 1474 * PCI_ANY_ID. 1475 */ 1476 #define PCI_DEVICE(vend, dev) \ 1477 .vendor = (vend), .device = (dev), \ 1478 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1479 1480 /** 1481 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 1482 * @vend: the 16 bit PCI Vendor ID 1483 * @dev: the 16 bit PCI Device ID 1484 * @subvend: the 16 bit PCI Subvendor ID 1485 * @subdev: the 16 bit PCI Subdevice ID 1486 * 1487 * This macro is used to create a struct pci_device_id that matches a 1488 * specific device with subsystem information. 1489 */ 1490 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1491 .vendor = (vend), .device = (dev), \ 1492 .subvendor = (subvend), .subdevice = (subdev) 1493 1494 /** 1495 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 1496 * @dev_class: the class, subclass, prog-if triple for this device 1497 * @dev_class_mask: the class mask for this device 1498 * 1499 * This macro is used to create a struct pci_device_id that matches a 1500 * specific PCI class. The vendor, device, subvendor, and subdevice 1501 * fields will be set to PCI_ANY_ID. 1502 */ 1503 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ 1504 .class = (dev_class), .class_mask = (dev_class_mask), \ 1505 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1506 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1507 1508 /** 1509 * PCI_VDEVICE - macro used to describe a specific pci device in short form 1510 * @vend: the vendor name 1511 * @dev: the 16 bit PCI Device ID 1512 * 1513 * This macro is used to create a struct pci_device_id that matches a 1514 * specific PCI device. The subvendor, and subdevice fields will be set 1515 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1516 * private data. 1517 */ 1518 1519 #define PCI_VDEVICE(vend, dev) \ 1520 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1521 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1522 1523 /** 1524 * struct pci_driver_entry - Matches a driver to its pci_device_id list 1525 * @driver: Driver to use 1526 * @match: List of match records for this driver, terminated by {} 1527 */ 1528 struct pci_driver_entry { 1529 struct driver *driver; 1530 const struct pci_device_id *match; 1531 }; 1532 1533 #define U_BOOT_PCI_DEVICE(__name, __match) \ 1534 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\ 1535 .driver = llsym(struct driver, __name, driver), \ 1536 .match = __match, \ 1537 } 1538 1539 #endif /* __ASSEMBLY__ */ 1540 #endif /* _PCI_H */ 1541
