1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2011 Andes Technology Corp 4 * Macpaul Lin <macpaul (at) andestech.com> 5 */ 6 7 /* 8 * Andes Power Control Unit 9 */ 10 #ifndef __ANDES_PCU_H 11 #define __ANDES_PCU_H 12 13 #ifndef __ASSEMBLY__ 14 15 struct pcs { 16 unsigned int cr; /* PCSx Configuration (clock scaling) */ 17 unsigned int parm; /* PCSx Parameter*/ 18 unsigned int stat1; /* PCSx Status 1 */ 19 unsigned int stat2; /* PCSx Stusts 2 */ 20 unsigned int pdd; /* PCSx PDD */ 21 }; 22 23 struct andes_pcu { 24 unsigned int rev; /* 0x00 - PCU Revision */ 25 unsigned int spinfo; /* 0x04 - Scratch Pad Info */ 26 unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */ 27 unsigned int soc_id; /* 0x10 - SoC ID */ 28 unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */ 29 unsigned int soc_apb; /* 0x18 - SoC APB configuration */ 30 unsigned int rsvd2; /* 0x1C */ 31 unsigned int dcsrcr0; /* 0x20 - Driving Capability 32 and Slew Rate Control 0 */ 33 unsigned int dcsrcr1; /* 0x24 - Driving Capability 34 and Slew Rate Control 1 */ 35 unsigned int dcsrcr2; /* 0x28 - Driving Capability 36 and Slew Rate Control 2 */ 37 unsigned int rsvd3; /* 0x2C */ 38 unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */ 39 unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */ 40 unsigned int dmaes; /* 0x38 - DMA Engine Selection */ 41 unsigned int rsvd4; /* 0x3C */ 42 unsigned int oscc; /* 0x40 - OSC Control */ 43 unsigned int pwmcd; /* 0x44 - PWM Clock divider */ 44 unsigned int socmisc; /* 0x48 - SoC Misc. */ 45 unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */ 46 unsigned int bsmcr; /* 0x80 - BSM Controrl */ 47 unsigned int bsmst; /* 0x84 - BSM Status */ 48 unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/ 49 unsigned int west; /* 0x8C - Wakeup Event Status */ 50 unsigned int rsttiming; /* 0x90 - Reset Timing */ 51 unsigned int intr_st; /* 0x94 - PCU Interrupt Status */ 52 unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */ 53 struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */ 54 unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */ 55 struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */ 56 unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */ 57 struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */ 58 unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */ 59 struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */ 60 unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */ 61 struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */ 62 unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */ 63 struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */ 64 unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */ 65 struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */ 66 unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */ 67 struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */ 68 unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */ 69 struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */ 70 unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */ 71 unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager 72 Scratch Pad Memory 0 */ 73 }; 74 #endif /* __ASSEMBLY__ */ 75 76 /* 77 * PCU Revision Register (ro) 78 */ 79 #define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) 80 #define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) 81 82 /* 83 * Scratch Pad Info Register (ro) 84 */ 85 #define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) 86 #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) 87 88 /* 89 * SoC ID Register (ro) 90 */ 91 #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) 92 #define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) 93 #define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) 94 95 /* 96 * SoC AHB Configuration Register (ro) 97 */ 98 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) 99 #define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) 100 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) 101 #define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3) 102 #define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4) 103 #define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5) 104 #define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6) 105 #define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7) 106 #define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8) 107 #define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) 108 #define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12) 109 #define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13) 110 #define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14) 111 #define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15) 112 #define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16) 113 #define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17) 114 #define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18) 115 #define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19) 116 #define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20) 117 #define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27) 118 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28) 119 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29) 120 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30) 121 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31) 122 123 /* 124 * SoC APB Configuration Register (ro) 125 */ 126 #define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) 127 #define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) 128 #define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3) 129 #define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) 130 #define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6) 131 #define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8) 132 #define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) 133 #define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) 134 #define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) 135 #define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19) 136 #define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20) 137 #define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22) 138 #define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23) 139 140 /* 141 * Driving Capability and Slew Rate Control Register 0 (rw) 142 */ 143 #define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0) 144 #define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8) 145 #define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12) 146 #define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16) 147 #define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20) 148 149 /* 150 * Driving Capability and Slew Rate Control Register 1 (rw) 151 */ 152 #define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0) 153 154 /* 155 * Driving Capability and Slew Rate Control Register 2 (rw) 156 */ 157 #define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0) 158 #define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4) 159 #define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8) 160 #define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12) 161 #define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16) 162 #define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20) 163 #define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24) 164 #define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28) 165 166 /* 167 * Multi-function Port Setting Register 0 (rw) 168 */ 169 #define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0) 170 #define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1) 171 #define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2) 172 #define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3) 173 #define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4) 174 #define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28) 175 #define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31) 176 177 /* 178 * Multi-function Port Setting Register 1 (rw) 179 */ 180 #define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0) 181 #define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1) 182 #define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2) 183 #define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3) 184 #define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4) 185 #define ANDES_PCU_MFPSR1_PME(x) ((x) << 5) 186 #define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6) 187 #define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7) 188 #define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8) 189 #define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9) 190 #define ANDES_PCU_MFPSR1_SD(x) ((x) << 10) 191 #define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27) 192 #define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28) 193 #define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29) 194 #define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30) 195 #define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31) 196 197 /* 198 * DMA Engine Selection Register (rw) 199 */ 200 #define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2) 201 #define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3) 202 #define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4) 203 #define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5) 204 #define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6) 205 #define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7) 206 #define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8) 207 #define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9) 208 209 /* 210 * OSC Control Register (rw) 211 */ 212 #define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0) 213 #define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1) 214 #define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2) 215 #define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4) 216 #define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6) 217 #define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8) 218 219 /* 220 * PWM Clock Divider Register (rw) 221 */ 222 #define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0) 223 224 /* 225 * SoC Misc. Register (rw) 226 */ 227 #define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0) 228 #define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1) 229 #define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2) 230 #define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3) 231 #define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4) 232 #define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6) 233 #define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8) 234 #define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9) 235 #define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10) 236 #define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11) 237 #define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12) 238 #define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13) 239 #define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14) 240 #define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15) 241 #define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16) 242 #define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17) 243 #define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18) 244 #define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19) 245 #define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20) 246 #define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21) 247 #define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22) 248 #define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23) 249 #define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24) 250 #define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25) 251 #define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26) 252 #define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27) 253 #define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28) 254 #define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29) 255 #define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30) 256 #define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31) 257 258 /* 259 * BSM Control Register (rw) 260 */ 261 #define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0) 262 #define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4) 263 #define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24) 264 #define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28) 265 #define ANDES_PCU_BSMCR_IE(x) ((x) << 31) 266 267 /* 268 * BSM Status Register 269 */ 270 #define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0) 271 #define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4) 272 #define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24) 273 #define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28) 274 275 /* 276 * Wakeup Event Sensitivity Register (rw) 277 */ 278 #define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0) 279 280 /* 281 * Wakeup Event Status Register (ro) 282 */ 283 #define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0) 284 285 /* 286 * Reset Timing Register 287 */ 288 #define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0) 289 #define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8) 290 #define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16) 291 #define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24) 292 293 /* 294 * PCU Interrupt Status Register 295 */ 296 #define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0) 297 #define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1) 298 #define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2) 299 #define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3) 300 #define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4) 301 #define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5) 302 #define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6) 303 #define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7) 304 #define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8) 305 #define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9) 306 307 /* 308 * PCSx Configuration Register 309 */ 310 #define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0) 311 #define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16) 312 #define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20) 313 #define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */ 314 315 /* 316 * PCSx Parameter Register (rw) 317 */ 318 #define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0) 319 #define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24) 320 #define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28) 321 #define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31) 322 323 /* 324 * PCSx Status Register 1 325 */ 326 #define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0) 327 #define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28) 328 329 /* 330 * PCSx Status Register 2 331 */ 332 #define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0) 333 #define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24) 334 335 /* 336 * PCSx PDD Register 337 * This is reserved for PCS(1-7) 338 */ 339 #define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0) 340 #define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8) 341 #define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16) 342 #define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24) 343 344 #define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0) 345 #define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6) 346 #define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12) 347 #define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18) 348 #define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24) 349 #define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27) 350 #define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28) 351 #define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30) 352 #define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31) 353 354 #endif /* __ANDES_PCU_H */ 355
