1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PMU_COM_H__ 8 #define __PMU_COM_H__ 9 10 #ifndef CHECK_CPU_WFIE_BASE 11 #define CHECK_CPU_WFIE_BASE (PMU_BASE + PMU_CORE_PWR_ST) 12 #endif 13 /* 14 * Use this macro to instantiate lock before it is used in below 15 * rockchip_pd_lock_xxx() macros 16 */ 17 DECLARE_BAKERY_LOCK(rockchip_pd_lock); 18 19 /* 20 * These are wrapper macros to the powe domain Bakery Lock API. 21 */ 22 #define rockchip_pd_lock_init() bakery_lock_init(&rockchip_pd_lock) 23 #define rockchip_pd_lock_get() bakery_lock_get(&rockchip_pd_lock) 24 #define rockchip_pd_lock_rls() bakery_lock_release(&rockchip_pd_lock) 25 26 /***************************************************************************** 27 * power domain on or off 28 *****************************************************************************/ 29 enum pmu_pd_state { 30 pmu_pd_on = 0, 31 pmu_pd_off = 1 32 }; 33 34 #pragma weak plat_ic_get_pending_interrupt_id 35 #pragma weak pmu_power_domain_ctr 36 #pragma weak check_cpu_wfie 37 38 static inline uint32_t pmu_power_domain_st(uint32_t pd) 39 { 40 uint32_t pwrdn_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd); 41 42 if (pwrdn_st) 43 return pmu_pd_off; 44 else 45 return pmu_pd_on; 46 } 47 48 static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) 49 { 50 uint32_t val; 51 uint32_t loop = 0; 52 int ret = 0; 53 54 rockchip_pd_lock_get(); 55 56 val = mmio_read_32(PMU_BASE + PMU_PWRDN_CON); 57 if (pd_state == pmu_pd_off) 58 val |= BIT(pd); 59 else 60 val &= ~BIT(pd); 61 62 mmio_write_32(PMU_BASE + PMU_PWRDN_CON, val); 63 dsb(); 64 65 while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { 66 udelay(1); 67 loop++; 68 } 69 70 if (pmu_power_domain_st(pd) != pd_state) { 71 WARN("%s: %d, %d, error!\n", __func__, pd, pd_state); 72 ret = -EINVAL; 73 } 74 75 rockchip_pd_lock_rls(); 76 77 return ret; 78 } 79 80 static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk) 81 { 82 uint32_t cluster_id, loop = 0; 83 84 if (cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT) { 85 cluster_id = 1; 86 cpu_id -= PLATFORM_CLUSTER0_CORE_COUNT; 87 } else { 88 cluster_id = 0; 89 } 90 91 if (cluster_id) 92 wfie_msk <<= (clstb_cpu_wfe + cpu_id); 93 else 94 wfie_msk <<= (clstl_cpu_wfe + cpu_id); 95 96 while (!(mmio_read_32(CHECK_CPU_WFIE_BASE) & wfie_msk) && 97 (loop < CHK_CPU_LOOP)) { 98 udelay(1); 99 loop++; 100 } 101 102 if ((mmio_read_32(CHECK_CPU_WFIE_BASE) & wfie_msk) == 0) { 103 WARN("%s: %d, %d, %d, error!\n", __func__, 104 cluster_id, cpu_id, wfie_msk); 105 return -EINVAL; 106 } 107 108 return 0; 109 } 110 111 #endif /* __PMU_COM_H__ */ 112