1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <debug.h> 9 #include <platform.h> 10 #include <platform_def.h> 11 #include "psci_private.h" 12 13 #ifndef PLAT_MAX_PWR_LVL_STATES 14 #define PLAT_MAX_PWR_LVL_STATES 2 15 #endif 16 17 /* Following structure is used for PSCI STAT */ 18 typedef struct psci_stat { 19 u_register_t residency; 20 u_register_t count; 21 } psci_stat_t; 22 23 /* 24 * Following is used to keep track of the last cpu 25 * that goes to power down in non cpu power domains. 26 */ 27 static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {-1}; 28 29 /* 30 * Following are used to store PSCI STAT values for 31 * CPU and non CPU power domains. 32 */ 33 static psci_stat_t psci_cpu_stat[PLATFORM_CORE_COUNT] 34 [PLAT_MAX_PWR_LVL_STATES]; 35 static psci_stat_t psci_non_cpu_stat[PSCI_NUM_NON_CPU_PWR_DOMAINS] 36 [PLAT_MAX_PWR_LVL_STATES]; 37 38 /* 39 * This functions returns the index into the `psci_stat_t` array given the 40 * local power state and power domain level. If the platform implements the 41 * `get_pwr_lvl_state_idx` pm hook, then that will be used to return the index. 42 */ 43 static int get_stat_idx(plat_local_state_t local_state, int pwr_lvl) 44 { 45 int idx; 46 47 if (psci_plat_pm_ops->get_pwr_lvl_state_idx == NULL) { 48 assert(PLAT_MAX_PWR_LVL_STATES == 2); 49 if (is_local_state_retn(local_state)) 50 return 0; 51 52 assert(is_local_state_off(local_state)); 53 return 1; 54 } 55 56 idx = psci_plat_pm_ops->get_pwr_lvl_state_idx(local_state, pwr_lvl); 57 assert((idx >= 0) && (idx < PLAT_MAX_PWR_LVL_STATES)); 58 return idx; 59 } 60 61 /******************************************************************************* 62 * This function is passed the target local power states for each power 63 * domain (state_info) between the current CPU domain and its ancestors until 64 * the target power level (end_pwrlvl). 65 * 66 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it 67 * updates the `last_cpu_in_non_cpu_pd[]` with last power down cpu id. 68 * 69 * This function will only be invoked with data cache enabled and while 70 * powering down a core. 71 ******************************************************************************/ 72 void psci_stats_update_pwr_down(unsigned int end_pwrlvl, 73 const psci_power_state_t *state_info) 74 { 75 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); 76 77 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); 78 assert(state_info); 79 80 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 81 82 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { 83 84 /* Break early if the target power state is RUN */ 85 if (is_local_state_run(state_info->pwr_domain_state[lvl])) 86 break; 87 88 /* 89 * The power domain is entering a low power state, so this is 90 * the last CPU for this power domain 91 */ 92 last_cpu_in_non_cpu_pd[parent_idx] = cpu_idx; 93 94 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 95 } 96 97 } 98 99 /******************************************************************************* 100 * This function updates the PSCI STATS(residency time and count) for CPU 101 * and NON-CPU power domains. 102 * It is called with caches enabled and locks acquired(for NON-CPU domain) 103 ******************************************************************************/ 104 void psci_stats_update_pwr_up(unsigned int end_pwrlvl, 105 const psci_power_state_t *state_info) 106 { 107 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); 108 int stat_idx; 109 plat_local_state_t local_state; 110 u_register_t residency; 111 112 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); 113 assert(state_info); 114 115 /* Get the index into the stats array */ 116 local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; 117 stat_idx = get_stat_idx(local_state, PSCI_CPU_PWR_LVL); 118 119 /* Call into platform interface to calculate residency. */ 120 residency = plat_psci_stat_get_residency(PSCI_CPU_PWR_LVL, 121 state_info, cpu_idx); 122 123 /* Update CPU stats. */ 124 psci_cpu_stat[cpu_idx][stat_idx].residency += residency; 125 psci_cpu_stat[cpu_idx][stat_idx].count++; 126 127 /* 128 * Check what power domains above CPU were off 129 * prior to this CPU powering on. 130 */ 131 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 132 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { 133 local_state = state_info->pwr_domain_state[lvl]; 134 if (is_local_state_run(local_state)) { 135 /* Break early */ 136 break; 137 } 138 139 assert(last_cpu_in_non_cpu_pd[parent_idx] != -1); 140 141 /* Call into platform interface to calculate residency. */ 142 residency = plat_psci_stat_get_residency(lvl, state_info, 143 last_cpu_in_non_cpu_pd[parent_idx]); 144 145 /* Initialize back to reset value */ 146 last_cpu_in_non_cpu_pd[parent_idx] = -1; 147 148 /* Get the index into the stats array */ 149 stat_idx = get_stat_idx(local_state, lvl); 150 151 /* Update non cpu stats */ 152 psci_non_cpu_stat[parent_idx][stat_idx].residency += residency; 153 psci_non_cpu_stat[parent_idx][stat_idx].count++; 154 155 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 156 } 157 158 } 159 160 /******************************************************************************* 161 * This function returns the appropriate count and residency time of the 162 * local state for the highest power level expressed in the `power_state` 163 * for the node represented by `target_cpu`. 164 ******************************************************************************/ 165 static int psci_get_stat(u_register_t target_cpu, unsigned int power_state, 166 psci_stat_t *psci_stat) 167 { 168 int rc; 169 unsigned int pwrlvl, lvl, parent_idx, stat_idx, target_idx; 170 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 171 plat_local_state_t local_state; 172 173 /* Validate the target_cpu parameter and determine the cpu index */ 174 target_idx = plat_core_pos_by_mpidr(target_cpu); 175 if (target_idx == -1) 176 return PSCI_E_INVALID_PARAMS; 177 178 /* Validate the power_state parameter */ 179 if (!psci_plat_pm_ops->translate_power_state_by_mpidr) 180 rc = psci_validate_power_state(power_state, &state_info); 181 else 182 rc = psci_plat_pm_ops->translate_power_state_by_mpidr( 183 target_cpu, power_state, &state_info); 184 185 if (rc != PSCI_E_SUCCESS) 186 return PSCI_E_INVALID_PARAMS; 187 188 /* Find the highest power level */ 189 pwrlvl = psci_find_target_suspend_lvl(&state_info); 190 if (pwrlvl == PSCI_INVALID_PWR_LVL) { 191 ERROR("Invalid target power level for PSCI statistics operation\n"); 192 panic(); 193 } 194 195 /* Get the index into the stats array */ 196 local_state = state_info.pwr_domain_state[pwrlvl]; 197 stat_idx = get_stat_idx(local_state, pwrlvl); 198 199 if (pwrlvl > PSCI_CPU_PWR_LVL) { 200 /* Get the power domain index */ 201 parent_idx = psci_cpu_pd_nodes[target_idx].parent_node; 202 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl < pwrlvl; lvl++) 203 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 204 205 /* Get the non cpu power domain stats */ 206 *psci_stat = psci_non_cpu_stat[parent_idx][stat_idx]; 207 } else { 208 /* Get the cpu power domain stats */ 209 *psci_stat = psci_cpu_stat[target_idx][stat_idx]; 210 } 211 212 return PSCI_E_SUCCESS; 213 } 214 215 /* This is the top level function for PSCI_STAT_RESIDENCY SMC. */ 216 u_register_t psci_stat_residency(u_register_t target_cpu, 217 unsigned int power_state) 218 { 219 psci_stat_t psci_stat; 220 int rc = psci_get_stat(target_cpu, power_state, &psci_stat); 221 222 if (rc == PSCI_E_SUCCESS) 223 return psci_stat.residency; 224 else 225 return 0; 226 } 227 228 /* This is the top level function for PSCI_STAT_COUNT SMC. */ 229 u_register_t psci_stat_count(u_register_t target_cpu, 230 unsigned int power_state) 231 { 232 psci_stat_t psci_stat; 233 int rc = psci_get_stat(target_cpu, power_state, &psci_stat); 234 235 if (rc == PSCI_E_SUCCESS) 236 return psci_stat.count; 237 else 238 return 0; 239 } 240
