1 /* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude (at) gmail.com> 3 * Copyright 2009 Marek Olk <maraeo (at) gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24 /* r300_emit: Functions for emitting state. */ 25 26 #include "util/u_format.h" 27 #include "util/u_math.h" 28 29 #include "r300_context.h" 30 #include "r300_cb.h" 31 #include "r300_cs.h" 32 #include "r300_emit.h" 33 #include "r300_fs.h" 34 #include "r300_screen.h" 35 #include "r300_screen_buffer.h" 36 #include "r300_vs.h" 37 38 void r300_emit_blend_state(struct r300_context* r300, 39 unsigned size, void* state) 40 { 41 struct r300_blend_state* blend = (struct r300_blend_state*)state; 42 struct pipe_framebuffer_state* fb = 43 (struct pipe_framebuffer_state*)r300->fb_state.state; 44 struct pipe_surface *cb; 45 CS_LOCALS(r300); 46 47 cb = fb->nr_cbufs ? r300_get_nonnull_cb(fb, 0) : NULL; 48 49 if (cb) { 50 if (cb->format == PIPE_FORMAT_R16G16B16A16_FLOAT) { 51 WRITE_CS_TABLE(blend->cb_noclamp, size); 52 } else if (cb->format == PIPE_FORMAT_R16G16B16X16_FLOAT) { 53 WRITE_CS_TABLE(blend->cb_noclamp_noalpha, size); 54 } else { 55 unsigned swz = r300_surface(cb)->colormask_swizzle; 56 WRITE_CS_TABLE(blend->cb_clamp[swz], size); 57 } 58 } else { 59 WRITE_CS_TABLE(blend->cb_no_readwrite, size); 60 } 61 } 62 63 void r300_emit_blend_color_state(struct r300_context* r300, 64 unsigned size, void* state) 65 { 66 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state; 67 CS_LOCALS(r300); 68 69 WRITE_CS_TABLE(bc->cb, size); 70 } 71 72 void r300_emit_clip_state(struct r300_context* r300, 73 unsigned size, void* state) 74 { 75 struct r300_clip_state* clip = (struct r300_clip_state*)state; 76 CS_LOCALS(r300); 77 78 WRITE_CS_TABLE(clip->cb, size); 79 } 80 81 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state) 82 { 83 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state; 84 struct pipe_framebuffer_state* fb = 85 (struct pipe_framebuffer_state*)r300->fb_state.state; 86 boolean is_r500 = r300->screen->caps.is_r500; 87 CS_LOCALS(r300); 88 uint32_t alpha_func = dsa->alpha_function; 89 90 /* Choose the alpha ref value between 8-bit (FG_ALPHA_FUNC.AM_VAL) and 91 * 16-bit (FG_ALPHA_VALUE). */ 92 if (is_r500 && (alpha_func & R300_FG_ALPHA_FUNC_ENABLE)) { 93 struct pipe_surface *cb = fb->nr_cbufs ? r300_get_nonnull_cb(fb, 0) : NULL; 94 95 if (cb && 96 (cb->format == PIPE_FORMAT_R16G16B16A16_FLOAT || 97 cb->format == PIPE_FORMAT_R16G16B16X16_FLOAT)) { 98 alpha_func |= R500_FG_ALPHA_FUNC_FP16_ENABLE; 99 } else { 100 alpha_func |= R500_FG_ALPHA_FUNC_8BIT; 101 } 102 } 103 104 /* Setup alpha-to-coverage. */ 105 if (r300->alpha_to_coverage && r300->msaa_enable) { 106 /* Always set 3/6, it improves precision even for 2x and 4x MSAA. */ 107 alpha_func |= R300_FG_ALPHA_FUNC_MASK_ENABLE | 108 R300_FG_ALPHA_FUNC_CFG_3_OF_6; 109 } 110 111 BEGIN_CS(size); 112 OUT_CS_REG(R300_FG_ALPHA_FUNC, alpha_func); 113 OUT_CS_TABLE(fb->zsbuf ? &dsa->cb_begin : dsa->cb_zb_no_readwrite, size-2); 114 END_CS; 115 } 116 117 static void get_rc_constant_state( 118 float vec[4], 119 struct r300_context * r300, 120 struct rc_constant * constant) 121 { 122 struct r300_textures_state* texstate = r300->textures_state.state; 123 struct r300_resource *tex; 124 125 assert(constant->Type == RC_CONSTANT_STATE); 126 127 /* vec should either be (0, 0, 0, 1), which should be a relatively safe 128 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE 129 * state factors. */ 130 131 switch (constant->u.State[0]) { 132 /* Factor for converting rectangle coords to 133 * normalized coords. Should only show up on non-r500. */ 134 case RC_STATE_R300_TEXRECT_FACTOR: 135 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture); 136 vec[0] = 1.0 / tex->tex.width0; 137 vec[1] = 1.0 / tex->tex.height0; 138 vec[2] = 0; 139 vec[3] = 1; 140 break; 141 142 case RC_STATE_R300_TEXSCALE_FACTOR: 143 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture); 144 /* Add a small number to the texture size to work around rounding errors in hw. */ 145 vec[0] = tex->b.b.width0 / (tex->tex.width0 + 0.001f); 146 vec[1] = tex->b.b.height0 / (tex->tex.height0 + 0.001f); 147 vec[2] = tex->b.b.depth0 / (tex->tex.depth0 + 0.001f); 148 vec[3] = 1; 149 break; 150 151 case RC_STATE_R300_VIEWPORT_SCALE: 152 vec[0] = r300->viewport.scale[0]; 153 vec[1] = r300->viewport.scale[1]; 154 vec[2] = r300->viewport.scale[2]; 155 vec[3] = 1; 156 break; 157 158 case RC_STATE_R300_VIEWPORT_OFFSET: 159 vec[0] = r300->viewport.translate[0]; 160 vec[1] = r300->viewport.translate[1]; 161 vec[2] = r300->viewport.translate[2]; 162 vec[3] = 1; 163 break; 164 165 default: 166 fprintf(stderr, "r300: Implementation error: " 167 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]); 168 vec[0] = 0; 169 vec[1] = 0; 170 vec[2] = 0; 171 vec[3] = 1; 172 } 173 } 174 175 /* Convert a normal single-precision float into the 7.16 format 176 * used by the R300 fragment shader. 177 */ 178 uint32_t pack_float24(float f) 179 { 180 union { 181 float fl; 182 uint32_t u; 183 } u; 184 float mantissa; 185 int exponent; 186 uint32_t float24 = 0; 187 188 if (f == 0.0) 189 return 0; 190 191 u.fl = f; 192 193 mantissa = frexpf(f, &exponent); 194 195 /* Handle -ve */ 196 if (mantissa < 0) { 197 float24 |= (1 << 23); 198 mantissa = mantissa * -1.0; 199 } 200 /* Handle exponent, bias of 63 */ 201 exponent += 62; 202 float24 |= (exponent << 16); 203 /* Kill 7 LSB of mantissa */ 204 float24 |= (u.u & 0x7FFFFF) >> 7; 205 206 return float24; 207 } 208 209 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state) 210 { 211 struct r300_fragment_shader *fs = r300_fs(r300); 212 CS_LOCALS(r300); 213 214 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size); 215 } 216 217 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state) 218 { 219 struct r300_fragment_shader *fs = r300_fs(r300); 220 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state; 221 unsigned count = fs->shader->externals_count; 222 unsigned i, j; 223 CS_LOCALS(r300); 224 225 if (count == 0) 226 return; 227 228 BEGIN_CS(size); 229 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4); 230 if (buf->remap_table){ 231 for (i = 0; i < count; i++) { 232 float *data = (float*)&buf->ptr[buf->remap_table[i]*4]; 233 for (j = 0; j < 4; j++) 234 OUT_CS(pack_float24(data[j])); 235 } 236 } else { 237 for (i = 0; i < count; i++) 238 for (j = 0; j < 4; j++) 239 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j])); 240 } 241 242 END_CS; 243 } 244 245 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state) 246 { 247 struct r300_fragment_shader *fs = r300_fs(r300); 248 struct rc_constant_list *constants = &fs->shader->code.constants; 249 unsigned i; 250 unsigned count = fs->shader->rc_state_count; 251 unsigned first = fs->shader->externals_count; 252 unsigned end = constants->Count; 253 unsigned j; 254 CS_LOCALS(r300); 255 256 if (count == 0) 257 return; 258 259 BEGIN_CS(size); 260 for(i = first; i < end; ++i) { 261 if (constants->Constants[i].Type == RC_CONSTANT_STATE) { 262 float data[4]; 263 264 get_rc_constant_state(data, r300, &constants->Constants[i]); 265 266 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4); 267 for (j = 0; j < 4; j++) 268 OUT_CS(pack_float24(data[j])); 269 } 270 } 271 END_CS; 272 } 273 274 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state) 275 { 276 struct r300_fragment_shader *fs = r300_fs(r300); 277 CS_LOCALS(r300); 278 279 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size); 280 } 281 282 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state) 283 { 284 struct r300_fragment_shader *fs = r300_fs(r300); 285 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state; 286 unsigned count = fs->shader->externals_count; 287 CS_LOCALS(r300); 288 289 if (count == 0) 290 return; 291 292 BEGIN_CS(size); 293 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST); 294 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4); 295 if (buf->remap_table){ 296 for (unsigned i = 0; i < count; i++) { 297 uint32_t *data = &buf->ptr[buf->remap_table[i]*4]; 298 OUT_CS_TABLE(data, 4); 299 } 300 } else { 301 OUT_CS_TABLE(buf->ptr, count * 4); 302 } 303 END_CS; 304 } 305 306 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state) 307 { 308 struct r300_fragment_shader *fs = r300_fs(r300); 309 struct rc_constant_list *constants = &fs->shader->code.constants; 310 unsigned i; 311 unsigned count = fs->shader->rc_state_count; 312 unsigned first = fs->shader->externals_count; 313 unsigned end = constants->Count; 314 CS_LOCALS(r300); 315 316 if (count == 0) 317 return; 318 319 BEGIN_CS(size); 320 for(i = first; i < end; ++i) { 321 if (constants->Constants[i].Type == RC_CONSTANT_STATE) { 322 float data[4]; 323 324 get_rc_constant_state(data, r300, &constants->Constants[i]); 325 326 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, 327 R500_GA_US_VECTOR_INDEX_TYPE_CONST | 328 (i & R500_GA_US_VECTOR_INDEX_MASK)); 329 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4); 330 OUT_CS_TABLE(data, 4); 331 } 332 } 333 END_CS; 334 } 335 336 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state) 337 { 338 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state; 339 struct pipe_framebuffer_state* fb = 340 (struct pipe_framebuffer_state*)r300->fb_state.state; 341 uint32_t height = fb->height; 342 uint32_t width = fb->width; 343 CS_LOCALS(r300); 344 345 if (r300->cbzb_clear) { 346 struct r300_surface *surf = r300_surface(fb->cbufs[0]); 347 348 height = surf->cbzb_height; 349 width = surf->cbzb_width; 350 } 351 352 DBG(r300, DBG_SCISSOR, 353 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n", 354 width, height, r300->cbzb_clear ? "YES" : "NO"); 355 356 BEGIN_CS(size); 357 358 /* Set up scissors. 359 * By writing to the SC registers, SC & US assert idle. */ 360 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2); 361 if (r300->screen->caps.is_r500) { 362 OUT_CS(0); 363 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) | 364 ((height - 1) << R300_SCISSORS_Y_SHIFT)); 365 } else { 366 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) | 367 (1440 << R300_SCISSORS_Y_SHIFT)); 368 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) | 369 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT)); 370 } 371 372 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */ 373 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6); 374 END_CS; 375 } 376 377 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state) 378 { 379 struct r300_aa_state *aa = (struct r300_aa_state*)state; 380 CS_LOCALS(r300); 381 382 BEGIN_CS(size); 383 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config); 384 385 if (aa->dest) { 386 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 3); 387 OUT_CS(aa->dest->offset); 388 OUT_CS(aa->dest->pitch & R300_RB3D_AARESOLVE_PITCH_MASK); 389 OUT_CS(R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE | 390 R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE); 391 OUT_CS_RELOC(aa->dest); 392 } else { 393 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0); 394 } 395 396 END_CS; 397 } 398 399 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state) 400 { 401 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state; 402 struct r300_surface* surf; 403 unsigned i; 404 uint32_t rb3d_cctl = 0; 405 406 CS_LOCALS(r300); 407 408 BEGIN_CS(size); 409 410 if (r300->screen->caps.is_r500) { 411 rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE; 412 } 413 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers. */ 414 if (fb->nr_cbufs && r300->fb_multiwrite) { 415 rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs); 416 } 417 if (r300->cmask_in_use) { 418 rb3d_cctl |= R300_RB3D_CCTL_AA_COMPRESSION_ENABLE | 419 R300_RB3D_CCTL_CMASK_ENABLE; 420 } 421 422 OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl); 423 424 /* Set up colorbuffers. */ 425 for (i = 0; i < fb->nr_cbufs; i++) { 426 surf = r300_surface(r300_get_nonnull_cb(fb, i)); 427 428 OUT_CS_REG(R300_RB3D_COLOROFFSET0 + (4 * i), surf->offset); 429 OUT_CS_RELOC(surf); 430 431 OUT_CS_REG(R300_RB3D_COLORPITCH0 + (4 * i), surf->pitch); 432 OUT_CS_RELOC(surf); 433 434 if (r300->cmask_in_use && i == 0) { 435 OUT_CS_REG(R300_RB3D_CMASK_OFFSET0, 0); 436 OUT_CS_REG(R300_RB3D_CMASK_PITCH0, surf->pitch_cmask); 437 OUT_CS_REG(R300_RB3D_COLOR_CLEAR_VALUE, r300->color_clear_value); 438 if (r300->screen->caps.is_r500 && r300->screen->info.drm_minor >= 29) { 439 OUT_CS_REG_SEQ(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2); 440 OUT_CS(r300->color_clear_value_ar); 441 OUT_CS(r300->color_clear_value_gb); 442 } 443 } 444 } 445 446 /* Set up the ZB part of the CBZB clear. */ 447 if (r300->cbzb_clear) { 448 surf = r300_surface(fb->cbufs[0]); 449 450 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format); 451 452 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->cbzb_midpoint_offset); 453 OUT_CS_RELOC(surf); 454 455 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->cbzb_pitch); 456 OUT_CS_RELOC(surf); 457 458 DBG(r300, DBG_CBZB, 459 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format, 460 surf->cbzb_pitch); 461 } 462 /* Set up a zbuffer. */ 463 else if (fb->zsbuf) { 464 surf = r300_surface(fb->zsbuf); 465 466 OUT_CS_REG(R300_ZB_FORMAT, surf->format); 467 468 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->offset); 469 OUT_CS_RELOC(surf); 470 471 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch); 472 OUT_CS_RELOC(surf); 473 474 if (r300->hyperz_enabled) { 475 /* HiZ RAM. */ 476 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0); 477 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz); 478 /* Z Mask RAM. (compressed zbuffer) */ 479 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0); 480 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf->pitch_zmask); 481 } 482 } 483 484 END_CS; 485 } 486 487 void r300_emit_hyperz_state(struct r300_context *r300, 488 unsigned size, void *state) 489 { 490 struct r300_hyperz_state *z = state; 491 CS_LOCALS(r300); 492 493 if (z->flush) 494 WRITE_CS_TABLE(&z->cb_flush_begin, size); 495 else 496 WRITE_CS_TABLE(&z->cb_begin, size - 2); 497 } 498 499 void r300_emit_hyperz_end(struct r300_context *r300) 500 { 501 struct r300_hyperz_state z = 502 *(struct r300_hyperz_state*)r300->hyperz_state.state; 503 504 z.flush = 1; 505 z.zb_bw_cntl = 0; 506 z.zb_depthclearvalue = 0; 507 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2; 508 z.gb_z_peq_config = 0; 509 510 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z); 511 } 512 513 #define R300_NIBBLES(x0, y0, x1, y1, x2, y2, d0y, d0x) \ 514 (((x0) & 0xf) | (((y0) & 0xf) << 4) | \ 515 (((x1) & 0xf) << 8) | (((y1) & 0xf) << 12) | \ 516 (((x2) & 0xf) << 16) | (((y2) & 0xf) << 20) | \ 517 (((d0y) & 0xf) << 24) | (((d0x) & 0xf) << 28)) 518 519 static unsigned r300_get_mspos(int index, unsigned *p) 520 { 521 unsigned reg, i, distx, disty, dist; 522 523 if (index == 0) { 524 /* MSPOS0 contains positions for samples 0,1,2 as (X,Y) pairs of nibbles, 525 * followed by a (Y,X) pair containing the minimum distance from the pixel 526 * edge: 527 * X0, Y0, X1, Y1, X2, Y2, D0_Y, D0_X 528 * 529 * There is a quirk when setting D0_X. The value represents the distance 530 * from the left edge of the pixel quad to the first sample in subpixels. 531 * All values less than eight should use the actual value, but 7 should 532 * be used for the distance 8. The hardware will convert 7 into 8 internally. 533 */ 534 distx = 11; 535 for (i = 0; i < 12; i += 2) { 536 if (p[i] < distx) 537 distx = p[i]; 538 } 539 540 disty = 11; 541 for (i = 1; i < 12; i += 2) { 542 if (p[i] < disty) 543 disty = p[i]; 544 } 545 546 if (distx == 8) 547 distx = 7; 548 549 reg = R300_NIBBLES(p[0], p[1], p[2], p[3], p[4], p[5], disty, distx); 550 } else { 551 /* MSPOS1 contains positions for samples 3,4,5 as (X,Y) pairs of nibbles, 552 * followed by the minimum distance from the pixel edge (not sure if X or Y): 553 * X3, Y3, X4, Y4, X5, Y5, D1 554 */ 555 dist = 11; 556 for (i = 0; i < 12; i++) { 557 if (p[i] < dist) 558 dist = p[i]; 559 } 560 561 reg = R300_NIBBLES(p[6], p[7], p[8], p[9], p[10], p[11], dist, 0); 562 } 563 return reg; 564 } 565 566 void r300_emit_fb_state_pipelined(struct r300_context *r300, 567 unsigned size, void *state) 568 { 569 /* The sample coordinates are in the range [0,11], because 570 * GB_TILE_CONFIG.SUBPIXEL is set to the 1/12 subpixel precision. 571 * 572 * Some sample coordinates reach to neighboring pixels and should not be used. 573 * (e.g. Y=11) 574 * 575 * The unused samples must be set to the positions of other valid samples. */ 576 static unsigned sample_locs_1x[12] = { 577 6,6, 6,6, 6,6, 6,6, 6,6, 6,6 578 }; 579 static unsigned sample_locs_2x[12] = { 580 3,9, 9,3, 9,3, 9,3, 9,3, 9,3 581 }; 582 static unsigned sample_locs_4x[12] = { 583 4,4, 8,8, 2,10, 10,2, 10,2, 10,2 584 }; 585 static unsigned sample_locs_6x[12] = { 586 3,1, 7,3, 11,5, 1,7, 5,9, 9,10 587 }; 588 589 struct pipe_framebuffer_state* fb = 590 (struct pipe_framebuffer_state*)r300->fb_state.state; 591 unsigned i, num_cbufs = fb->nr_cbufs; 592 unsigned mspos0, mspos1; 593 CS_LOCALS(r300); 594 595 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be 596 * marked as UNUSED in the US block. */ 597 if (r300->fb_multiwrite) { 598 num_cbufs = MIN2(num_cbufs, 1); 599 } 600 601 BEGIN_CS(size); 602 603 /* Colorbuffer format in the US block. 604 * (must be written after unpipelined regs) */ 605 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4); 606 for (i = 0; i < num_cbufs; i++) { 607 OUT_CS(r300_surface(r300_get_nonnull_cb(fb, i))->format); 608 } 609 for (; i < 1; i++) { 610 OUT_CS(R300_US_OUT_FMT_C4_8 | 611 R300_C0_SEL_B | R300_C1_SEL_G | 612 R300_C2_SEL_R | R300_C3_SEL_A); 613 } 614 for (; i < 4; i++) { 615 OUT_CS(R300_US_OUT_FMT_UNUSED); 616 } 617 618 /* Set sample positions. It depends on the framebuffer sample count. 619 * These are pipelined regs and as such cannot be moved to the AA state. 620 */ 621 switch (r300->num_samples) { 622 default: 623 mspos0 = r300_get_mspos(0, sample_locs_1x); 624 mspos1 = r300_get_mspos(1, sample_locs_1x); 625 break; 626 case 2: 627 mspos0 = r300_get_mspos(0, sample_locs_2x); 628 mspos1 = r300_get_mspos(1, sample_locs_2x); 629 break; 630 case 4: 631 mspos0 = r300_get_mspos(0, sample_locs_4x); 632 mspos1 = r300_get_mspos(1, sample_locs_4x); 633 break; 634 case 6: 635 mspos0 = r300_get_mspos(0, sample_locs_6x); 636 mspos1 = r300_get_mspos(1, sample_locs_6x); 637 break; 638 } 639 640 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2); 641 OUT_CS(mspos0); 642 OUT_CS(mspos1); 643 END_CS; 644 } 645 646 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state) 647 { 648 struct r300_query *query = r300->query_current; 649 CS_LOCALS(r300); 650 651 if (!query) 652 return; 653 654 BEGIN_CS(size); 655 if (r300->screen->caps.family == CHIP_RV530) { 656 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); 657 } else { 658 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL); 659 } 660 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0); 661 END_CS; 662 query->begin_emitted = TRUE; 663 } 664 665 static void r300_emit_query_end_frag_pipes(struct r300_context *r300, 666 struct r300_query *query) 667 { 668 struct r300_capabilities* caps = &r300->screen->caps; 669 uint32_t gb_pipes = r300->screen->info.r300_num_gb_pipes; 670 CS_LOCALS(r300); 671 672 assert(gb_pipes); 673 674 BEGIN_CS(6 * gb_pipes + 2); 675 /* I'm not so sure I like this switch, but it's hard to be elegant 676 * when there's so many special cases... 677 * 678 * So here's the basic idea. For each pipe, enable writes to it only, 679 * then put out the relocation for ZPASS_ADDR, taking into account a 680 * 4-byte offset for each pipe. RV380 and older are special; they have 681 * only two pipes, and the second pipe's enable is on bit 3, not bit 1, 682 * so there's a chipset cap for that. */ 683 switch (gb_pipes) { 684 case 4: 685 /* pipe 3 only */ 686 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3); 687 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 3) * 4); 688 OUT_CS_RELOC(r300->query_current); 689 case 3: 690 /* pipe 2 only */ 691 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2); 692 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 2) * 4); 693 OUT_CS_RELOC(r300->query_current); 694 case 2: 695 /* pipe 1 only */ 696 /* As mentioned above, accommodate RV380 and older. */ 697 OUT_CS_REG(R300_SU_REG_DEST, 698 1 << (caps->high_second_pipe ? 3 : 1)); 699 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4); 700 OUT_CS_RELOC(r300->query_current); 701 case 1: 702 /* pipe 0 only */ 703 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0); 704 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4); 705 OUT_CS_RELOC(r300->query_current); 706 break; 707 default: 708 fprintf(stderr, "r300: Implementation error: Chipset reports %d" 709 " pixel pipes!\n", gb_pipes); 710 abort(); 711 } 712 713 /* And, finally, reset it to normal... */ 714 OUT_CS_REG(R300_SU_REG_DEST, 0xF); 715 END_CS; 716 } 717 718 static void rv530_emit_query_end_single_z(struct r300_context *r300, 719 struct r300_query *query) 720 { 721 CS_LOCALS(r300); 722 723 BEGIN_CS(8); 724 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0); 725 OUT_CS_REG(R300_ZB_ZPASS_ADDR, query->num_results * 4); 726 OUT_CS_RELOC(r300->query_current); 727 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); 728 END_CS; 729 } 730 731 static void rv530_emit_query_end_double_z(struct r300_context *r300, 732 struct r300_query *query) 733 { 734 CS_LOCALS(r300); 735 736 BEGIN_CS(14); 737 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0); 738 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4); 739 OUT_CS_RELOC(r300->query_current); 740 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1); 741 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4); 742 OUT_CS_RELOC(r300->query_current); 743 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); 744 END_CS; 745 } 746 747 void r300_emit_query_end(struct r300_context* r300) 748 { 749 struct r300_capabilities *caps = &r300->screen->caps; 750 struct r300_query *query = r300->query_current; 751 752 if (!query) 753 return; 754 755 if (query->begin_emitted == FALSE) 756 return; 757 758 if (caps->family == CHIP_RV530) { 759 if (r300->screen->info.r300_num_z_pipes == 2) 760 rv530_emit_query_end_double_z(r300, query); 761 else 762 rv530_emit_query_end_single_z(r300, query); 763 } else 764 r300_emit_query_end_frag_pipes(r300, query); 765 766 query->begin_emitted = FALSE; 767 query->num_results += query->num_pipes; 768 769 /* XXX grab all the results and reset the counter. */ 770 if (query->num_results >= query->buf->size / 4 - 4) { 771 query->num_results = (query->buf->size / 4) / 2; 772 fprintf(stderr, "r300: Rewinding OQBO...\n"); 773 } 774 } 775 776 void r300_emit_invariant_state(struct r300_context *r300, 777 unsigned size, void *state) 778 { 779 CS_LOCALS(r300); 780 WRITE_CS_TABLE(state, size); 781 } 782 783 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state) 784 { 785 struct r300_rs_state* rs = state; 786 CS_LOCALS(r300); 787 788 BEGIN_CS(size); 789 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE); 790 if (rs->polygon_offset_enable) { 791 if (r300->zbuffer_bpp == 16) { 792 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5); 793 } else { 794 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5); 795 } 796 } 797 END_CS; 798 } 799 800 void r300_emit_rs_block_state(struct r300_context* r300, 801 unsigned size, void* state) 802 { 803 struct r300_rs_block* rs = (struct r300_rs_block*)state; 804 unsigned i; 805 /* It's the same for both INST and IP tables */ 806 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1; 807 CS_LOCALS(r300); 808 809 if (DBG_ON(r300, DBG_RS_BLOCK)) { 810 r500_dump_rs_block(rs); 811 812 fprintf(stderr, "r300: RS emit:\n"); 813 814 for (i = 0; i < count; i++) 815 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]); 816 817 for (i = 0; i < count; i++) 818 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]); 819 820 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n", 821 rs->count, rs->inst_count); 822 } 823 824 BEGIN_CS(size); 825 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2); 826 OUT_CS(rs->vap_vtx_state_cntl); 827 OUT_CS(rs->vap_vsm_vtx_assm); 828 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2); 829 OUT_CS(rs->vap_out_vtx_fmt[0]); 830 OUT_CS(rs->vap_out_vtx_fmt[1]); 831 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1); 832 OUT_CS(rs->gb_enable); 833 834 if (r300->screen->caps.is_r500) { 835 OUT_CS_REG_SEQ(R500_RS_IP_0, count); 836 } else { 837 OUT_CS_REG_SEQ(R300_RS_IP_0, count); 838 } 839 OUT_CS_TABLE(rs->ip, count); 840 841 OUT_CS_REG_SEQ(R300_RS_COUNT, 2); 842 OUT_CS(rs->count); 843 OUT_CS(rs->inst_count); 844 845 if (r300->screen->caps.is_r500) { 846 OUT_CS_REG_SEQ(R500_RS_INST_0, count); 847 } else { 848 OUT_CS_REG_SEQ(R300_RS_INST_0, count); 849 } 850 OUT_CS_TABLE(rs->inst, count); 851 END_CS; 852 } 853 854 void r300_emit_sample_mask(struct r300_context *r300, 855 unsigned size, void *state) 856 { 857 unsigned mask = (*(unsigned*)state) & ((1 << 6)-1); 858 CS_LOCALS(r300); 859 860 BEGIN_CS(size); 861 OUT_CS_REG(R300_SC_SCREENDOOR, 862 mask | (mask << 6) | (mask << 12) | (mask << 18)); 863 END_CS; 864 } 865 866 void r300_emit_scissor_state(struct r300_context* r300, 867 unsigned size, void* state) 868 { 869 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state; 870 CS_LOCALS(r300); 871 872 BEGIN_CS(size); 873 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2); 874 if (r300->screen->caps.is_r500) { 875 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) | 876 (scissor->miny << R300_CLIPRECT_Y_SHIFT)); 877 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) | 878 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT)); 879 } else { 880 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) | 881 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT)); 882 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) | 883 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT)); 884 } 885 END_CS; 886 } 887 888 void r300_emit_textures_state(struct r300_context *r300, 889 unsigned size, void *state) 890 { 891 struct r300_textures_state *allstate = (struct r300_textures_state*)state; 892 struct r300_texture_sampler_state *texstate; 893 struct r300_resource *tex; 894 unsigned i; 895 boolean has_us_format = r300->screen->caps.has_us_format; 896 CS_LOCALS(r300); 897 898 BEGIN_CS(size); 899 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable); 900 901 for (i = 0; i < allstate->count; i++) { 902 if ((1 << i) & allstate->tx_enable) { 903 texstate = &allstate->regs[i]; 904 tex = r300_resource(allstate->sampler_views[i]->base.texture); 905 906 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0); 907 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1); 908 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4), 909 texstate->border_color); 910 911 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0); 912 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1); 913 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2); 914 915 OUT_CS_REG(R300_TX_OFFSET_0 + (i * 4), texstate->format.tile_config); 916 OUT_CS_RELOC(tex); 917 918 if (has_us_format) { 919 OUT_CS_REG(R500_US_FORMAT0_0 + (i * 4), 920 texstate->format.us_format0); 921 } 922 } 923 } 924 END_CS; 925 } 926 927 void r300_emit_vertex_arrays(struct r300_context* r300, int offset, 928 boolean indexed, int instance_id) 929 { 930 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer; 931 struct pipe_vertex_element *velem = r300->velems->velem; 932 struct r300_resource *buf; 933 int i; 934 unsigned vertex_array_count = r300->velems->count; 935 unsigned packet_size = (vertex_array_count * 3 + 1) / 2; 936 struct pipe_vertex_buffer *vb1, *vb2; 937 unsigned *hw_format_size = r300->velems->format_size; 938 unsigned size1, size2, offset1, offset2, stride1, stride2; 939 CS_LOCALS(r300); 940 941 BEGIN_CS(2 + packet_size + vertex_array_count * 2); 942 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size); 943 OUT_CS(vertex_array_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0)); 944 945 if (instance_id == -1) { 946 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */ 947 for (i = 0; i < vertex_array_count - 1; i += 2) { 948 vb1 = &vbuf[velem[i].vertex_buffer_index]; 949 vb2 = &vbuf[velem[i+1].vertex_buffer_index]; 950 size1 = hw_format_size[i]; 951 size2 = hw_format_size[i+1]; 952 953 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) | 954 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride)); 955 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride); 956 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride); 957 } 958 959 if (vertex_array_count & 1) { 960 vb1 = &vbuf[velem[i].vertex_buffer_index]; 961 size1 = hw_format_size[i]; 962 963 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride)); 964 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride); 965 } 966 967 for (i = 0; i < vertex_array_count; i++) { 968 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer.resource); 969 OUT_CS_RELOC(buf); 970 } 971 } else { 972 /* Instanced arrays. */ 973 for (i = 0; i < vertex_array_count - 1; i += 2) { 974 vb1 = &vbuf[velem[i].vertex_buffer_index]; 975 vb2 = &vbuf[velem[i+1].vertex_buffer_index]; 976 size1 = hw_format_size[i]; 977 size2 = hw_format_size[i+1]; 978 979 if (velem[i].instance_divisor) { 980 stride1 = 0; 981 offset1 = vb1->buffer_offset + velem[i].src_offset + 982 (instance_id / velem[i].instance_divisor) * vb1->stride; 983 } else { 984 stride1 = vb1->stride; 985 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride; 986 } 987 if (velem[i+1].instance_divisor) { 988 stride2 = 0; 989 offset2 = vb2->buffer_offset + velem[i+1].src_offset + 990 (instance_id / velem[i+1].instance_divisor) * vb2->stride; 991 } else { 992 stride2 = vb2->stride; 993 offset2 = vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride; 994 } 995 996 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1) | 997 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(stride2)); 998 OUT_CS(offset1); 999 OUT_CS(offset2); 1000 } 1001 1002 if (vertex_array_count & 1) { 1003 vb1 = &vbuf[velem[i].vertex_buffer_index]; 1004 size1 = hw_format_size[i]; 1005 1006 if (velem[i].instance_divisor) { 1007 stride1 = 0; 1008 offset1 = vb1->buffer_offset + velem[i].src_offset + 1009 (instance_id / velem[i].instance_divisor) * vb1->stride; 1010 } else { 1011 stride1 = vb1->stride; 1012 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride; 1013 } 1014 1015 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1)); 1016 OUT_CS(offset1); 1017 } 1018 1019 for (i = 0; i < vertex_array_count; i++) { 1020 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer.resource); 1021 OUT_CS_RELOC(buf); 1022 } 1023 } 1024 END_CS; 1025 } 1026 1027 void r300_emit_vertex_arrays_swtcl(struct r300_context *r300, boolean indexed) 1028 { 1029 CS_LOCALS(r300); 1030 1031 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, " 1032 "vertex size %d\n", r300->vbo, 1033 r300->vertex_info.size); 1034 /* Set the pointer to our vertex buffer. The emitted values are this: 1035 * PACKET3 [3D_LOAD_VBPNTR] 1036 * COUNT [1] 1037 * FORMAT [size | stride << 8] 1038 * OFFSET [offset into BO] 1039 * VBPNTR [relocated BO] 1040 */ 1041 BEGIN_CS(7); 1042 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3); 1043 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0)); 1044 OUT_CS(r300->vertex_info.size | 1045 (r300->vertex_info.size << 8)); 1046 OUT_CS(r300->draw_vbo_offset); 1047 OUT_CS(0); 1048 1049 assert(r300->vbo); 1050 OUT_CS(0xc0001000); /* PKT3_NOP */ 1051 OUT_CS(r300->rws->cs_lookup_buffer(r300->cs, r300->vbo) * 4); 1052 END_CS; 1053 } 1054 1055 void r300_emit_vertex_stream_state(struct r300_context* r300, 1056 unsigned size, void* state) 1057 { 1058 struct r300_vertex_stream_state *streams = 1059 (struct r300_vertex_stream_state*)state; 1060 unsigned i; 1061 CS_LOCALS(r300); 1062 1063 if (DBG_ON(r300, DBG_PSC)) { 1064 fprintf(stderr, "r300: PSC emit:\n"); 1065 1066 for (i = 0; i < streams->count; i++) { 1067 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i, 1068 streams->vap_prog_stream_cntl[i]); 1069 } 1070 1071 for (i = 0; i < streams->count; i++) { 1072 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i, 1073 streams->vap_prog_stream_cntl_ext[i]); 1074 } 1075 } 1076 1077 BEGIN_CS(size); 1078 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count); 1079 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count); 1080 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count); 1081 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count); 1082 END_CS; 1083 } 1084 1085 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state) 1086 { 1087 CS_LOCALS(r300); 1088 1089 BEGIN_CS(size); 1090 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0); 1091 END_CS; 1092 } 1093 1094 void r300_emit_vap_invariant_state(struct r300_context *r300, 1095 unsigned size, void *state) 1096 { 1097 CS_LOCALS(r300); 1098 WRITE_CS_TABLE(state, size); 1099 } 1100 1101 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state) 1102 { 1103 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state; 1104 struct r300_vertex_program_code* code = &vs->code; 1105 struct r300_screen* r300screen = r300->screen; 1106 unsigned instruction_count = code->length / 4; 1107 1108 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72; 1109 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1); 1110 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1); 1111 unsigned temp_count = MAX2(code->num_temporaries, 1); 1112 1113 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count, 1114 vtx_mem_size / output_count, 10); 1115 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5); 1116 1117 CS_LOCALS(r300); 1118 1119 BEGIN_CS(size); 1120 1121 /* R300_VAP_PVS_CODE_CNTL_0 1122 * R300_VAP_PVS_CONST_CNTL 1123 * R300_VAP_PVS_CODE_CNTL_1 1124 * See the r5xx docs for instructions on how to use these. */ 1125 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) | 1126 R300_PVS_XYZW_VALID_INST(instruction_count - 1) | 1127 R300_PVS_LAST_INST(instruction_count - 1)); 1128 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, instruction_count - 1); 1129 1130 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); 1131 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length); 1132 OUT_CS_TABLE(code->body.d, code->length); 1133 1134 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) | 1135 R300_PVS_NUM_CNTLRS(pvs_num_controllers) | 1136 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) | 1137 R300_PVS_VF_MAX_VTX_NUM(12) | 1138 (r300->clip_halfz ? R300_DX_CLIP_SPACE_DEF : 0) | 1139 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0)); 1140 1141 /* Emit flow control instructions. Even if there are no fc instructions, 1142 * we still need to write the registers to make sure they are cleared. */ 1143 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops); 1144 if (r300screen->caps.is_r500) { 1145 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, R300_VS_MAX_FC_OPS * 2); 1146 OUT_CS_TABLE(code->fc_op_addrs.r500, R300_VS_MAX_FC_OPS * 2); 1147 } else { 1148 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, R300_VS_MAX_FC_OPS); 1149 OUT_CS_TABLE(code->fc_op_addrs.r300, R300_VS_MAX_FC_OPS); 1150 } 1151 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, R300_VS_MAX_FC_OPS); 1152 OUT_CS_TABLE(code->fc_loop_index, R300_VS_MAX_FC_OPS); 1153 1154 END_CS; 1155 } 1156 1157 void r300_emit_vs_constants(struct r300_context* r300, 1158 unsigned size, void *state) 1159 { 1160 unsigned count = 1161 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count; 1162 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state; 1163 struct r300_vertex_shader *vs = (struct r300_vertex_shader*)r300->vs_state.state; 1164 unsigned i; 1165 int imm_first = vs->externals_count; 1166 int imm_end = vs->code.constants.Count; 1167 int imm_count = vs->immediates_count; 1168 CS_LOCALS(r300); 1169 1170 BEGIN_CS(size); 1171 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 1172 R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) | 1173 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0))); 1174 if (vs->externals_count) { 1175 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 1176 (r300->screen->caps.is_r500 ? 1177 R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base); 1178 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4); 1179 if (buf->remap_table){ 1180 for (i = 0; i < count; i++) { 1181 uint32_t *data = &buf->ptr[buf->remap_table[i]*4]; 1182 OUT_CS_TABLE(data, 4); 1183 } 1184 } else { 1185 OUT_CS_TABLE(buf->ptr, count * 4); 1186 } 1187 } 1188 1189 /* Emit immediates. */ 1190 if (imm_count) { 1191 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 1192 (r300->screen->caps.is_r500 ? 1193 R500_PVS_CONST_START : R300_PVS_CONST_START) + 1194 buf->buffer_base + imm_first); 1195 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4); 1196 for (i = imm_first; i < imm_end; i++) { 1197 const float *data = vs->code.constants.Constants[i].u.Immediate; 1198 OUT_CS_TABLE(data, 4); 1199 } 1200 } 1201 END_CS; 1202 } 1203 1204 void r300_emit_viewport_state(struct r300_context* r300, 1205 unsigned size, void* state) 1206 { 1207 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state; 1208 CS_LOCALS(r300); 1209 1210 BEGIN_CS(size); 1211 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6); 1212 OUT_CS_TABLE(&viewport->xscale, 6); 1213 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control); 1214 END_CS; 1215 } 1216 1217 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state) 1218 { 1219 struct pipe_framebuffer_state *fb = 1220 (struct pipe_framebuffer_state*)r300->fb_state.state; 1221 struct r300_resource* tex; 1222 CS_LOCALS(r300); 1223 1224 tex = r300_resource(fb->zsbuf->texture); 1225 1226 BEGIN_CS(size); 1227 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2); 1228 OUT_CS(0); 1229 OUT_CS(tex->tex.hiz_dwords[fb->zsbuf->u.tex.level]); 1230 OUT_CS(r300->hiz_clear_value); 1231 END_CS; 1232 1233 /* Mark the current zbuffer's hiz ram as in use. */ 1234 r300->hiz_in_use = TRUE; 1235 r300->hiz_func = HIZ_FUNC_NONE; 1236 r300_mark_atom_dirty(r300, &r300->hyperz_state); 1237 } 1238 1239 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state) 1240 { 1241 struct pipe_framebuffer_state *fb = 1242 (struct pipe_framebuffer_state*)r300->fb_state.state; 1243 struct r300_resource *tex; 1244 CS_LOCALS(r300); 1245 1246 tex = r300_resource(fb->zsbuf->texture); 1247 1248 BEGIN_CS(size); 1249 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2); 1250 OUT_CS(0); 1251 OUT_CS(tex->tex.zmask_dwords[fb->zsbuf->u.tex.level]); 1252 OUT_CS(0); 1253 END_CS; 1254 1255 /* Mark the current zbuffer's zmask as in use. */ 1256 r300->zmask_in_use = TRUE; 1257 r300_mark_atom_dirty(r300, &r300->hyperz_state); 1258 } 1259 1260 void r300_emit_cmask_clear(struct r300_context *r300, unsigned size, void *state) 1261 { 1262 struct pipe_framebuffer_state *fb = 1263 (struct pipe_framebuffer_state*)r300->fb_state.state; 1264 struct r300_resource *tex; 1265 CS_LOCALS(r300); 1266 1267 tex = r300_resource(fb->cbufs[0]->texture); 1268 1269 BEGIN_CS(size); 1270 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_CMASK, 2); 1271 OUT_CS(0); 1272 OUT_CS(tex->tex.cmask_dwords); 1273 OUT_CS(0); 1274 END_CS; 1275 1276 /* Mark the current zbuffer's zmask as in use. */ 1277 r300->cmask_in_use = TRUE; 1278 r300_mark_fb_state_dirty(r300, R300_CHANGED_CMASK_ENABLE); 1279 } 1280 1281 void r300_emit_ztop_state(struct r300_context* r300, 1282 unsigned size, void* state) 1283 { 1284 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state; 1285 CS_LOCALS(r300); 1286 1287 BEGIN_CS(size); 1288 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top); 1289 END_CS; 1290 } 1291 1292 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state) 1293 { 1294 CS_LOCALS(r300); 1295 1296 BEGIN_CS(size); 1297 OUT_CS_REG(R300_TX_INVALTAGS, 0); 1298 END_CS; 1299 } 1300 1301 boolean r300_emit_buffer_validate(struct r300_context *r300, 1302 boolean do_validate_vertex_buffers, 1303 struct pipe_resource *index_buffer) 1304 { 1305 struct pipe_framebuffer_state *fb = 1306 (struct pipe_framebuffer_state*)r300->fb_state.state; 1307 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state; 1308 struct r300_textures_state *texstate = 1309 (struct r300_textures_state*)r300->textures_state.state; 1310 struct r300_resource *tex; 1311 unsigned i; 1312 boolean flushed = FALSE; 1313 1314 validate: 1315 if (r300->fb_state.dirty) { 1316 /* Color buffers... */ 1317 for (i = 0; i < fb->nr_cbufs; i++) { 1318 if (!fb->cbufs[i]) 1319 continue; 1320 tex = r300_resource(fb->cbufs[i]->texture); 1321 assert(tex && tex->buf && "cbuf is marked, but NULL!"); 1322 r300->rws->cs_add_buffer(r300->cs, tex->buf, 1323 RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED, 1324 r300_surface(fb->cbufs[i])->domain, 1325 tex->b.b.nr_samples > 1 ? 1326 RADEON_PRIO_COLOR_BUFFER_MSAA : 1327 RADEON_PRIO_COLOR_BUFFER); 1328 } 1329 /* ...depth buffer... */ 1330 if (fb->zsbuf) { 1331 tex = r300_resource(fb->zsbuf->texture); 1332 assert(tex && tex->buf && "zsbuf is marked, but NULL!"); 1333 r300->rws->cs_add_buffer(r300->cs, tex->buf, 1334 RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED, 1335 r300_surface(fb->zsbuf)->domain, 1336 tex->b.b.nr_samples > 1 ? 1337 RADEON_PRIO_DEPTH_BUFFER_MSAA : 1338 RADEON_PRIO_DEPTH_BUFFER); 1339 } 1340 } 1341 /* The AA resolve buffer. */ 1342 if (r300->aa_state.dirty) { 1343 if (aa->dest) { 1344 r300->rws->cs_add_buffer(r300->cs, aa->dest->buf, 1345 RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED, 1346 aa->dest->domain, 1347 RADEON_PRIO_COLOR_BUFFER); 1348 } 1349 } 1350 if (r300->textures_state.dirty) { 1351 /* ...textures... */ 1352 for (i = 0; i < texstate->count; i++) { 1353 if (!(texstate->tx_enable & (1 << i))) { 1354 continue; 1355 } 1356 1357 tex = r300_resource(texstate->sampler_views[i]->base.texture); 1358 r300->rws->cs_add_buffer(r300->cs, tex->buf, 1359 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED, 1360 tex->domain, RADEON_PRIO_SAMPLER_TEXTURE); 1361 } 1362 } 1363 /* ...occlusion query buffer... */ 1364 if (r300->query_current) 1365 r300->rws->cs_add_buffer(r300->cs, r300->query_current->buf, 1366 RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED, 1367 RADEON_DOMAIN_GTT, 1368 RADEON_PRIO_QUERY); 1369 /* ...vertex buffer for SWTCL path... */ 1370 if (r300->vbo) 1371 r300->rws->cs_add_buffer(r300->cs, r300->vbo, 1372 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED, 1373 RADEON_DOMAIN_GTT, 1374 RADEON_PRIO_VERTEX_BUFFER); 1375 /* ...vertex buffers for HWTCL path... */ 1376 if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) { 1377 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer; 1378 struct pipe_vertex_buffer *last = r300->vertex_buffer + 1379 r300->nr_vertex_buffers; 1380 struct pipe_resource *buf; 1381 1382 for (; vbuf != last; vbuf++) { 1383 buf = vbuf->buffer.resource; 1384 if (!buf) 1385 continue; 1386 1387 r300->rws->cs_add_buffer(r300->cs, r300_resource(buf)->buf, 1388 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED, 1389 r300_resource(buf)->domain, 1390 RADEON_PRIO_SAMPLER_BUFFER); 1391 } 1392 } 1393 /* ...and index buffer for HWTCL path. */ 1394 if (index_buffer) 1395 r300->rws->cs_add_buffer(r300->cs, r300_resource(index_buffer)->buf, 1396 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED, 1397 r300_resource(index_buffer)->domain, 1398 RADEON_PRIO_INDEX_BUFFER); 1399 1400 /* Now do the validation (flush is called inside cs_validate on failure). */ 1401 if (!r300->rws->cs_validate(r300->cs)) { 1402 /* Ooops, an infinite loop, give up. */ 1403 if (flushed) 1404 return FALSE; 1405 1406 flushed = TRUE; 1407 goto validate; 1408 } 1409 1410 return TRUE; 1411 } 1412 1413 unsigned r300_get_num_dirty_dwords(struct r300_context *r300) 1414 { 1415 struct r300_atom* atom; 1416 unsigned dwords = 0; 1417 1418 foreach_dirty_atom(r300, atom) { 1419 if (atom->dirty) { 1420 dwords += atom->size; 1421 } 1422 } 1423 1424 /* let's reserve some more, just in case */ 1425 dwords += 32; 1426 1427 return dwords; 1428 } 1429 1430 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300) 1431 { 1432 unsigned dwords = 0; 1433 1434 /* Emitted in flush. */ 1435 dwords += 26; /* emit_query_end */ 1436 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */ 1437 if (r300->screen->caps.is_r500) 1438 dwords += 2; /* emit_index_bias */ 1439 dwords += 3; /* MSPOS */ 1440 1441 return dwords; 1442 } 1443 1444 /* Emit all dirty state. */ 1445 void r300_emit_dirty_state(struct r300_context* r300) 1446 { 1447 struct r300_atom *atom; 1448 1449 foreach_dirty_atom(r300, atom) { 1450 if (atom->dirty) { 1451 atom->emit(r300, atom->size, atom->state); 1452 atom->dirty = FALSE; 1453 } 1454 } 1455 1456 r300->first_dirty = NULL; 1457 r300->last_dirty = NULL; 1458 r300->dirty_hw++; 1459 } 1460
