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    Searched defs:rcw (Results 1 - 7 of 7) sorted by null

  /external/u-boot/drivers/ddr/fsl/
ddr3_dimm_params.c 141 u8 rcw = spd->mod_section.registered.rcw[i/2]; local
142 pdimm->rcw[i] = (rcw >> 0) & 0x0F;
143 pdimm->rcw[i+1] = (rcw >> 4) & 0x0F;
  /external/u-boot/include/
common_timing_params.h 65 unsigned char rcw[16]; /* Register Control Word 0-15 */ member in struct:__anon47639
fsl_ddr_dimm_params.h 108 unsigned char rcw[16]; /* Register Control Word 0-15 */ member in struct:dimm_params_s
ddr_spd.h 263 unsigned char rcw[8]; member in struct:ddr3_spd_eeprom_s::__anon47644::__anon47646
  /external/u-boot/arch/powerpc/cpu/mpc85xx/
cpu.c 53 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
273 /* Display the RCW, so that no one gets confused as to what RCW
276 puts("Reset Configuration Word (RCW):");
278 u32 rcw = in_be32(&gur->rcwsr[i]); local
282 printf(" %08x", rcw);
  /external/u-boot/arch/arm/cpu/armv7/ls102xa/
cpu.c 273 /* Display the RCW, so that no one gets confused as to what RCW
276 puts("Reset Configuration Word (RCW):");
278 u32 rcw = in_be32(&gur->rcwsr[i]); local
282 printf(" %08x", rcw);
  /external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
cpu.c 415 u32 type, rcw, svr = gur_in32(&gur->svr); local
451 * Display the RCW, so that no one gets confused as to what RCW
454 puts("Reset Configuration Word (RCW):");
456 rcw = gur_in32(&gur->rcwsr[i]);
459 printf(" %08x", rcw);

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