1 /* 2 * Copyright 2010 Intel Corporation 3 * Copyright 2011 Bryan Cain 4 * Copyright 2017 Gert Wollny 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef ST_GLSL_TO_TGSI_PRIVATE_H 27 #define ST_GLSL_TO_TGSI_PRIVATE_H 28 29 #include <mesa/main/mtypes.h> 30 #include <compiler/glsl_types.h> 31 #include <compiler/glsl/ir.h> 32 #include <tgsi/tgsi_info.h> 33 34 int swizzle_for_size(int size); 35 36 class st_dst_reg; 37 /** 38 * This struct is a corresponding struct to TGSI ureg_src. 39 */ 40 class st_src_reg { 41 public: 42 st_src_reg(gl_register_file file, int index, const glsl_type *type, 43 int component = 0, unsigned array_id = 0); 44 45 st_src_reg(gl_register_file file, int index, enum glsl_base_type type); 46 47 st_src_reg(gl_register_file file, int index, enum glsl_base_type type, int index2D); 48 49 st_src_reg(); 50 st_src_reg(const st_src_reg ®); 51 void operator=(const st_src_reg ®); 52 53 explicit st_src_reg(st_dst_reg reg); 54 55 st_src_reg get_abs(); 56 57 int32_t index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */ 58 int16_t index2D; 59 60 uint16_t swizzle; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */ 61 int negate:4; /**< NEGATE_XYZW mask from mesa */ 62 unsigned abs:1; 63 enum glsl_base_type type:6; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */ 64 unsigned has_index2:1; 65 gl_register_file file:5; /**< PROGRAM_* from Mesa */ 66 /* 67 * Is this the second half of a double register pair? 68 * currently used for input mapping only. 69 */ 70 unsigned double_reg2:1; 71 unsigned is_double_vertex_input:1; 72 unsigned array_id:10; 73 /** Register index should be offset by the integer in this reg. */ 74 st_src_reg *reladdr; 75 st_src_reg *reladdr2; 76 77 bool is_legal_tgsi_address_operand() const 78 { 79 /* 2D registers can't be used as an address operand, or if the address 80 * operand itself is a result of indirect addressing. 81 */ 82 return (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT) && 83 !has_index2 && !reladdr && !reladdr2; 84 } 85 }; 86 87 class st_dst_reg { 88 public: 89 st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type, int index); 90 91 st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type); 92 93 st_dst_reg(); 94 st_dst_reg(const st_dst_reg ®); 95 void operator=(const st_dst_reg ®); 96 97 explicit st_dst_reg(st_src_reg reg); 98 99 int32_t index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */ 100 int16_t index2D; 101 gl_register_file file:5; /**< PROGRAM_* from Mesa */ 102 unsigned writemask:4; /**< Bitfield of WRITEMASK_[XYZW] */ 103 enum glsl_base_type type:6; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */ 104 unsigned has_index2:1; 105 unsigned array_id:10; 106 107 /** Register index should be offset by the integer in this reg. */ 108 st_src_reg *reladdr; 109 st_src_reg *reladdr2; 110 }; 111 112 class glsl_to_tgsi_instruction : public exec_node { 113 public: 114 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction) 115 116 st_dst_reg dst[2]; 117 st_src_reg src[4]; 118 st_src_reg resource; /**< sampler or buffer register */ 119 st_src_reg *tex_offsets; 120 121 /** Pointer to the ir source this tree came fe02549fdrom for debugging */ 122 ir_instruction *ir; 123 124 unsigned op:8; /**< TGSI opcode */ 125 unsigned precise:1; 126 unsigned saturate:1; 127 unsigned is_64bit_expanded:1; 128 unsigned sampler_base:5; 129 unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if not array */ 130 gl_texture_index tex_target:5; 131 glsl_base_type tex_type:6; 132 unsigned tex_shadow:1; 133 enum pipe_format image_format:10; 134 unsigned tex_offset_num_offset:3; 135 unsigned dead_mask:4; /**< Used in dead code elimination */ 136 unsigned buffer_access:3; /**< bitmask of TGSI_MEMORY_x bits */ 137 138 const struct tgsi_opcode_info *info; 139 }; 140 141 struct rename_reg_pair { 142 bool valid; 143 int new_reg; 144 }; 145 146 inline static bool 147 is_resource_instruction(unsigned opcode) 148 { 149 switch (opcode) { 150 case TGSI_OPCODE_RESQ: 151 case TGSI_OPCODE_LOAD: 152 case TGSI_OPCODE_ATOMUADD: 153 case TGSI_OPCODE_ATOMXCHG: 154 case TGSI_OPCODE_ATOMCAS: 155 case TGSI_OPCODE_ATOMAND: 156 case TGSI_OPCODE_ATOMOR: 157 case TGSI_OPCODE_ATOMXOR: 158 case TGSI_OPCODE_ATOMUMIN: 159 case TGSI_OPCODE_ATOMUMAX: 160 case TGSI_OPCODE_ATOMIMIN: 161 case TGSI_OPCODE_ATOMIMAX: 162 return true; 163 default: 164 return false; 165 } 166 } 167 168 inline static unsigned 169 num_inst_dst_regs(const glsl_to_tgsi_instruction *op) 170 { 171 return op->info->num_dst; 172 } 173 174 inline static unsigned 175 num_inst_src_regs(const glsl_to_tgsi_instruction *op) 176 { 177 return op->info->is_tex || is_resource_instruction(op->op) ? 178 op->info->num_src - 1 : op->info->num_src; 179 } 180 #endif 181
