| /external/vixl/src/aarch64/ |
| assembler-aarch64.cc | 997 void Assembler::rev16(const Register& rd, const Register& rn) { function in class:vixl::aarch64::Assembler
998 DataProcessing1Source(rd, rn, REV16);
[all...] |
| logic-aarch64.cc | 2132 LogicVRegister Simulator::rev16(VectorFormat vform, function in class:vixl::aarch64::Simulator
[all...] |
| /external/v8/src/arm64/ |
| simulator-logic-arm64.cc | 1913 LogicVRegister Simulator::rev16(VectorFormat vform, LogicVRegister dst, function in class:v8::internal::Simulator
[all...] |
| assembler-arm64.cc | 1563 void Assembler::rev16(const Register& rd, function in class:v8::internal::Assembler
2343 void Assembler::rev16(const VRegister& vd, const VRegister& vn) { function in class:v8::internal::Assembler
[all...] |
| /external/vixl/src/aarch32/ |
| assembler-aarch32.cc | 8861 void Assembler::rev16(Condition cond, function in class:vixl::aarch32::Assembler
[all...] |
| assembler-aarch32.h | 2867 void rev16(Register rd, Register rm) { rev16(al, Best, rd, rm); } function in class:vixl::aarch32::Assembler
2868 void rev16(Condition cond, Register rd, Register rm) { function in class:vixl::aarch32::Assembler
2871 void rev16(EncodingSize size, Register rd, Register rm) { function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.cc | 2270 void Disassembler::rev16(Condition cond, function in class:vixl::aarch32::Disassembler
[all...] |
