| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 33 rrx enumerator in enum:llvm::ARM_AM::ShiftOpc
52 case ARM_AM::rrx: return "rrx";
105 // reg [asr|lsl|lsr|ror|rrx] reg
106 // reg [asr|lsl|lsr|ror|rrx] imm
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 32 rrx enumerator in enum:llvm::ARM_AM::ShiftOpc
51 case ARM_AM::rrx: return "rrx";
104 // reg [asr|lsl|lsr|ror|rrx] reg
105 // reg [asr|lsl|lsr|ror|rrx] imm
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 33 rrx enumerator in enum:llvm::ARM_AM::ShiftOpc
50 case ARM_AM::rrx: return "rrx";
103 // reg [asr|lsl|lsr|ror|rrx] reg
104 // reg [asr|lsl|lsr|ror|rrx] imm
|
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_inline.h | 217 ANDS x7, mask, x7, rrx; local
401 "ands %1, %4, %1,rrx\n\t"
|
| /external/vixl/src/aarch32/ |
| assembler-aarch32.cc | 9043 void Assembler::rrx(Condition cond, Register rd, Register rm) { function in class:vixl::aarch32::Assembler
[all...] |
| assembler-aarch32.h | 2921 void rrx(Register rd, Register rm) { rrx(al, rd, rm); } function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.cc | 2316 void Disassembler::rrx(Condition cond, Register rd, Register rm) { function in class:vixl::aarch32::Disassembler
[all...] |
