1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2000-2009 4 * Viresh Kumar, ST Microelectronics, viresh.kumar (at) st.com 5 * Vipin Kumar, ST Microelectronics, vipin.kumar (at) st.com 6 */ 7 8 #include <common.h> 9 #include <asm/hardware.h> 10 #include <asm/io.h> 11 #include <asm/arch/spr_misc.h> 12 #include <asm/arch/spr_defs.h> 13 14 void spear_late_init(void) 15 { 16 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; 17 18 writel(0x80000007, &misc_p->arb_icm_ml1); 19 writel(0x80000007, &misc_p->arb_icm_ml2); 20 writel(0x80000007, &misc_p->arb_icm_ml3); 21 writel(0x80000007, &misc_p->arb_icm_ml4); 22 writel(0x80000007, &misc_p->arb_icm_ml5); 23 writel(0x80000007, &misc_p->arb_icm_ml6); 24 writel(0x80000007, &misc_p->arb_icm_ml7); 25 writel(0x80000007, &misc_p->arb_icm_ml8); 26 writel(0x80000007, &misc_p->arb_icm_ml9); 27 } 28 29 static void sel_1v8(void) 30 { 31 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; 32 u32 ddr1v8, ddr2v5; 33 34 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); 35 ddr2v5 &= 0x8080ffc0; 36 ddr2v5 |= 0x78000003; 37 writel(ddr2v5, &misc_p->ddr_2v5_compensation); 38 39 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); 40 ddr1v8 &= 0x8080ffc0; 41 ddr1v8 |= 0x78000010; 42 writel(ddr1v8, &misc_p->ddr_1v8_compensation); 43 44 while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE)) 45 ; 46 } 47 48 static void sel_2v5(void) 49 { 50 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; 51 u32 ddr1v8, ddr2v5; 52 53 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); 54 ddr1v8 &= 0x8080ffc0; 55 ddr1v8 |= 0x78000003; 56 writel(ddr1v8, &misc_p->ddr_1v8_compensation); 57 58 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); 59 ddr2v5 &= 0x8080ffc0; 60 ddr2v5 |= 0x78000010; 61 writel(ddr2v5, &misc_p->ddr_2v5_compensation); 62 63 while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE)) 64 ; 65 } 66 67 /* 68 * plat_ddr_init: 69 */ 70 void plat_ddr_init(void) 71 { 72 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; 73 u32 ddrpad; 74 u32 core3v3, ddr1v8, ddr2v5; 75 76 /* DDR pad register configurations */ 77 ddrpad = readl(&misc_p->ddr_pad); 78 ddrpad &= ~DDR_PAD_CNF_MSK; 79 80 #if (CONFIG_DDR_HCLK) 81 ddrpad |= 0xEAAB; 82 #elif (CONFIG_DDR_2HCLK) 83 ddrpad |= 0xEAAD; 84 #elif (CONFIG_DDR_PLL2) 85 ddrpad |= 0xEAAD; 86 #endif 87 writel(ddrpad, &misc_p->ddr_pad); 88 89 /* Compensation register configurations */ 90 core3v3 = readl(&misc_p->core_3v3_compensation); 91 core3v3 &= 0x8080ffe0; 92 core3v3 |= 0x78000002; 93 writel(core3v3, &misc_p->core_3v3_compensation); 94 95 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); 96 ddr1v8 &= 0x8080ffc0; 97 ddr1v8 |= 0x78000004; 98 writel(ddr1v8, &misc_p->ddr_1v8_compensation); 99 100 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); 101 ddr2v5 &= 0x8080ffc0; 102 ddr2v5 |= 0x78000004; 103 writel(ddr2v5, &misc_p->ddr_2v5_compensation); 104 105 if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) { 106 /* Software memory configuration */ 107 if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL) 108 sel_1v8(); 109 else 110 sel_2v5(); 111 } else { 112 /* Hardware memory configuration */ 113 if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE) 114 sel_1v8(); 115 else 116 sel_2v5(); 117 } 118 } 119 120 /* 121 * xxx_boot_selected: 122 * 123 * return true if the particular booting option is selected 124 * return false otherwise 125 */ 126 static u32 read_bootstrap(void) 127 { 128 return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT) 129 & CONFIG_SPEAR_BOOTSTRAPMASK; 130 } 131 132 int snor_boot_selected(void) 133 { 134 u32 bootstrap = read_bootstrap(); 135 136 if (SNOR_BOOT_SUPPORTED) { 137 /* Check whether SNOR boot is selected */ 138 if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) == 139 CONFIG_SPEAR_ONLYSNORBOOT) 140 return true; 141 142 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == 143 CONFIG_SPEAR_NORNAND8BOOT) 144 return true; 145 146 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == 147 CONFIG_SPEAR_NORNAND16BOOT) 148 return true; 149 } 150 151 return false; 152 } 153 154 int nand_boot_selected(void) 155 { 156 u32 bootstrap = read_bootstrap(); 157 158 if (NAND_BOOT_SUPPORTED) { 159 /* Check whether NAND boot is selected */ 160 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == 161 CONFIG_SPEAR_NORNAND8BOOT) 162 return true; 163 164 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == 165 CONFIG_SPEAR_NORNAND16BOOT) 166 return true; 167 } 168 169 return false; 170 } 171 172 int pnor_boot_selected(void) 173 { 174 /* Parallel NOR boot is not selected in any SPEAr600 revision */ 175 return false; 176 } 177 178 int usb_boot_selected(void) 179 { 180 u32 bootstrap = read_bootstrap(); 181 182 if (USB_BOOT_SUPPORTED) { 183 /* Check whether USB boot is selected */ 184 if (!(bootstrap & CONFIG_SPEAR_USBBOOT)) 185 return true; 186 } 187 188 return false; 189 } 190 191 int tftp_boot_selected(void) 192 { 193 /* TFTP boot is not selected in any SPEAr600 revision */ 194 return false; 195 } 196 197 int uart_boot_selected(void) 198 { 199 /* UART boot is not selected in any SPEAr600 revision */ 200 return false; 201 } 202 203 int spi_boot_selected(void) 204 { 205 /* SPI boot is not selected in any SPEAr600 revision */ 206 return false; 207 } 208 209 int i2c_boot_selected(void) 210 { 211 /* I2C boot is not selected in any SPEAr600 revision */ 212 return false; 213 } 214 215 int mmc_boot_selected(void) 216 { 217 return false; 218 } 219 220 void plat_late_init(void) 221 { 222 spear_late_init(); 223 } 224
