1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2010, CompuLab, Ltd. 4 * Author: Mike Rapoport <mike (at) compulab.co.il> 5 * 6 * Based on NVIDIA PCIe driver 7 * Copyright (c) 2008-2009, NVIDIA Corporation. 8 * 9 * Copyright (c) 2013-2014, NVIDIA Corporation. 10 */ 11 12 #define pr_fmt(fmt) "tegra-pcie: " fmt 13 14 #include <common.h> 15 #include <clk.h> 16 #include <dm.h> 17 #include <errno.h> 18 #include <malloc.h> 19 #include <pci.h> 20 #include <pci_tegra.h> 21 #include <power-domain.h> 22 #include <reset.h> 23 24 #include <asm/io.h> 25 #include <asm/gpio.h> 26 27 #include <linux/ioport.h> 28 #include <linux/list.h> 29 30 #ifndef CONFIG_TEGRA186 31 #include <asm/arch/clock.h> 32 #include <asm/arch/powergate.h> 33 #include <asm/arch-tegra/xusb-padctl.h> 34 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 35 #endif 36 37 /* 38 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that 39 * should not be present. These are needed because newer Tegra SoCs support 40 * only the standard clock/reset APIs, whereas older Tegra SoCs support only 41 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be 42 * fixed to implement the standard APIs, and all drivers converted to solely 43 * use the new standard APIs, with no ifdefs. 44 */ 45 46 #define AFI_AXI_BAR0_SZ 0x00 47 #define AFI_AXI_BAR1_SZ 0x04 48 #define AFI_AXI_BAR2_SZ 0x08 49 #define AFI_AXI_BAR3_SZ 0x0c 50 #define AFI_AXI_BAR4_SZ 0x10 51 #define AFI_AXI_BAR5_SZ 0x14 52 53 #define AFI_AXI_BAR0_START 0x18 54 #define AFI_AXI_BAR1_START 0x1c 55 #define AFI_AXI_BAR2_START 0x20 56 #define AFI_AXI_BAR3_START 0x24 57 #define AFI_AXI_BAR4_START 0x28 58 #define AFI_AXI_BAR5_START 0x2c 59 60 #define AFI_FPCI_BAR0 0x30 61 #define AFI_FPCI_BAR1 0x34 62 #define AFI_FPCI_BAR2 0x38 63 #define AFI_FPCI_BAR3 0x3c 64 #define AFI_FPCI_BAR4 0x40 65 #define AFI_FPCI_BAR5 0x44 66 67 #define AFI_CACHE_BAR0_SZ 0x48 68 #define AFI_CACHE_BAR0_ST 0x4c 69 #define AFI_CACHE_BAR1_SZ 0x50 70 #define AFI_CACHE_BAR1_ST 0x54 71 72 #define AFI_MSI_BAR_SZ 0x60 73 #define AFI_MSI_FPCI_BAR_ST 0x64 74 #define AFI_MSI_AXI_BAR_ST 0x68 75 76 #define AFI_CONFIGURATION 0xac 77 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 78 79 #define AFI_FPCI_ERROR_MASKS 0xb0 80 81 #define AFI_INTR_MASK 0xb4 82 #define AFI_INTR_MASK_INT_MASK (1 << 0) 83 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 84 85 #define AFI_SM_INTR_ENABLE 0xc4 86 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 87 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 88 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 89 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 90 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 91 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 92 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 93 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 94 95 #define AFI_AFI_INTR_ENABLE 0xc8 96 #define AFI_INTR_EN_INI_SLVERR (1 << 0) 97 #define AFI_INTR_EN_INI_DECERR (1 << 1) 98 #define AFI_INTR_EN_TGT_SLVERR (1 << 2) 99 #define AFI_INTR_EN_TGT_DECERR (1 << 3) 100 #define AFI_INTR_EN_TGT_WRERR (1 << 4) 101 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) 102 #define AFI_INTR_EN_AXI_DECERR (1 << 6) 103 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) 104 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) 105 106 #define AFI_PCIE_CONFIG 0x0f8 107 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 108 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe 109 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 110 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) 111 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) 112 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) 113 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) 114 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) 115 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) 116 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) 117 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20) 118 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20) 119 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20) 120 121 #define AFI_FUSE 0x104 122 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 123 124 #define AFI_PEX0_CTRL 0x110 125 #define AFI_PEX1_CTRL 0x118 126 #define AFI_PEX2_CTRL 0x128 127 #define AFI_PEX2_CTRL_T186 0x19c 128 #define AFI_PEX_CTRL_RST (1 << 0) 129 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 130 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 131 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 132 133 #define AFI_PLLE_CONTROL 0x160 134 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 135 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 136 137 #define AFI_PEXBIAS_CTRL_0 0x168 138 139 #define PADS_CTL_SEL 0x0000009C 140 141 #define PADS_CTL 0x000000A0 142 #define PADS_CTL_IDDQ_1L (1 << 0) 143 #define PADS_CTL_TX_DATA_EN_1L (1 << 6) 144 #define PADS_CTL_RX_DATA_EN_1L (1 << 10) 145 146 #define PADS_PLL_CTL_TEGRA20 0x000000B8 147 #define PADS_PLL_CTL_TEGRA30 0x000000B4 148 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1) 149 #define PADS_PLL_CTL_LOCKDET (0x1 << 8) 150 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) 151 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16) 152 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16) 153 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16) 154 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) 155 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20) 156 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20) 157 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22) 158 159 #define PADS_REFCLK_CFG0 0x000000C8 160 #define PADS_REFCLK_CFG1 0x000000CC 161 162 /* 163 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit 164 * entries, one entry per PCIe port. These field definitions and desired 165 * values aren't in the TRM, but do come from NVIDIA. 166 */ 167 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ 168 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 169 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ 170 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ 171 172 #define RP_VEND_XP 0x00000F00 173 #define RP_VEND_XP_DL_UP (1 << 30) 174 175 #define RP_VEND_CTL2 0x00000FA8 176 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) 177 178 #define RP_PRIV_MISC 0x00000FE0 179 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 180 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 181 182 #define RP_LINK_CONTROL_STATUS 0x00000090 183 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 184 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 185 186 enum tegra_pci_id { 187 TEGRA20_PCIE, 188 TEGRA30_PCIE, 189 TEGRA124_PCIE, 190 TEGRA210_PCIE, 191 TEGRA186_PCIE, 192 }; 193 194 struct tegra_pcie_port { 195 struct tegra_pcie *pcie; 196 197 struct fdt_resource regs; 198 unsigned int num_lanes; 199 unsigned int index; 200 201 struct list_head list; 202 }; 203 204 struct tegra_pcie_soc { 205 unsigned int num_ports; 206 unsigned long pads_pll_ctl; 207 unsigned long tx_ref_sel; 208 unsigned long afi_pex2_ctrl; 209 u32 pads_refclk_cfg0; 210 u32 pads_refclk_cfg1; 211 bool has_pex_clkreq_en; 212 bool has_pex_bias_ctrl; 213 bool has_cml_clk; 214 bool has_gen2; 215 bool force_pca_enable; 216 }; 217 218 struct tegra_pcie { 219 struct resource pads; 220 struct resource afi; 221 struct resource cs; 222 223 struct list_head ports; 224 unsigned long xbar; 225 226 const struct tegra_pcie_soc *soc; 227 228 #ifdef CONFIG_TEGRA186 229 struct clk clk_afi; 230 struct clk clk_pex; 231 struct reset_ctl reset_afi; 232 struct reset_ctl reset_pex; 233 struct reset_ctl reset_pcie_x; 234 struct power_domain pwrdom; 235 #else 236 struct tegra_xusb_phy *phy; 237 #endif 238 }; 239 240 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, 241 unsigned long offset) 242 { 243 writel(value, pcie->afi.start + offset); 244 } 245 246 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) 247 { 248 return readl(pcie->afi.start + offset); 249 } 250 251 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, 252 unsigned long offset) 253 { 254 writel(value, pcie->pads.start + offset); 255 } 256 257 #ifndef CONFIG_TEGRA186 258 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) 259 { 260 return readl(pcie->pads.start + offset); 261 } 262 #endif 263 264 static unsigned long rp_readl(struct tegra_pcie_port *port, 265 unsigned long offset) 266 { 267 return readl(port->regs.start + offset); 268 } 269 270 static void rp_writel(struct tegra_pcie_port *port, unsigned long value, 271 unsigned long offset) 272 { 273 writel(value, port->regs.start + offset); 274 } 275 276 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) 277 { 278 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | 279 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | 280 (where & 0xfc); 281 } 282 283 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, 284 int where, unsigned long *address) 285 { 286 unsigned int bus = PCI_BUS(bdf); 287 288 if (bus == 0) { 289 unsigned int dev = PCI_DEV(bdf); 290 struct tegra_pcie_port *port; 291 292 list_for_each_entry(port, &pcie->ports, list) { 293 if (port->index + 1 == dev) { 294 *address = port->regs.start + (where & ~3); 295 return 0; 296 } 297 } 298 return -EFAULT; 299 } else { 300 #ifdef CONFIG_TEGRA20 301 unsigned int dev = PCI_DEV(bdf); 302 if (dev != 0) 303 return -EFAULT; 304 #endif 305 306 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); 307 return 0; 308 } 309 } 310 311 static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf, 312 uint offset, ulong *valuep, 313 enum pci_size_t size) 314 { 315 struct tegra_pcie *pcie = dev_get_priv(bus); 316 unsigned long address, value; 317 int err; 318 319 err = tegra_pcie_conf_address(pcie, bdf, offset, &address); 320 if (err < 0) { 321 value = 0xffffffff; 322 goto done; 323 } 324 325 value = readl(address); 326 327 #ifdef CONFIG_TEGRA20 328 /* fixup root port class */ 329 if (PCI_BUS(bdf) == 0) { 330 if ((offset & ~3) == PCI_CLASS_REVISION) { 331 value &= ~0x00ff0000; 332 value |= PCI_CLASS_BRIDGE_PCI << 16; 333 } 334 } 335 #endif 336 337 done: 338 *valuep = pci_conv_32_to_size(value, offset, size); 339 340 return 0; 341 } 342 343 static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf, 344 uint offset, ulong value, 345 enum pci_size_t size) 346 { 347 struct tegra_pcie *pcie = dev_get_priv(bus); 348 unsigned long address; 349 ulong old; 350 int err; 351 352 err = tegra_pcie_conf_address(pcie, bdf, offset, &address); 353 if (err < 0) 354 return 0; 355 356 old = readl(address); 357 value = pci_conv_size_to_32(old, value, offset, size); 358 writel(value, address); 359 360 return 0; 361 } 362 363 static int tegra_pcie_port_parse_dt(ofnode node, struct tegra_pcie_port *port) 364 { 365 const u32 *addr; 366 int len; 367 368 addr = ofnode_get_property(node, "assigned-addresses", &len); 369 if (!addr) { 370 pr_err("property \"assigned-addresses\" not found"); 371 return -FDT_ERR_NOTFOUND; 372 } 373 374 port->regs.start = fdt32_to_cpu(addr[2]); 375 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]); 376 377 return 0; 378 } 379 380 static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes, 381 enum tegra_pci_id id, unsigned long *xbar) 382 { 383 switch (id) { 384 case TEGRA20_PCIE: 385 switch (lanes) { 386 case 0x00000004: 387 debug("single-mode configuration\n"); 388 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; 389 return 0; 390 391 case 0x00000202: 392 debug("dual-mode configuration\n"); 393 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; 394 return 0; 395 } 396 break; 397 case TEGRA30_PCIE: 398 switch (lanes) { 399 case 0x00000204: 400 debug("4x1, 2x1 configuration\n"); 401 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; 402 return 0; 403 404 case 0x00020202: 405 debug("2x3 configuration\n"); 406 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; 407 return 0; 408 409 case 0x00010104: 410 debug("4x1, 1x2 configuration\n"); 411 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; 412 return 0; 413 } 414 break; 415 case TEGRA124_PCIE: 416 case TEGRA210_PCIE: 417 switch (lanes) { 418 case 0x0000104: 419 debug("4x1, 1x1 configuration\n"); 420 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; 421 return 0; 422 423 case 0x0000102: 424 debug("2x1, 1x1 configuration\n"); 425 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; 426 return 0; 427 } 428 break; 429 case TEGRA186_PCIE: 430 switch (lanes) { 431 case 0x0010004: 432 debug("x4 x1 configuration\n"); 433 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401; 434 return 0; 435 436 case 0x0010102: 437 debug("x2 x1 x1 configuration\n"); 438 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211; 439 return 0; 440 441 case 0x0010101: 442 debug("x1 x1 x1 configuration\n"); 443 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111; 444 return 0; 445 } 446 break; 447 default: 448 break; 449 } 450 451 return -FDT_ERR_NOTFOUND; 452 } 453 454 static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes) 455 { 456 struct fdt_pci_addr addr; 457 int err; 458 459 err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1); 460 if (err < 0) { 461 pr_err("failed to parse \"nvidia,num-lanes\" property"); 462 return err; 463 } 464 465 *lanes = err; 466 467 err = ofnode_read_pci_addr(node, 0, "reg", &addr); 468 if (err < 0) { 469 pr_err("failed to parse \"reg\" property"); 470 return err; 471 } 472 473 *index = PCI_DEV(addr.phys_hi) - 1; 474 475 return 0; 476 } 477 478 int __weak tegra_pcie_board_init(void) 479 { 480 return 0; 481 } 482 483 static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id, 484 struct tegra_pcie *pcie) 485 { 486 ofnode subnode; 487 u32 lanes = 0; 488 int err; 489 490 err = dev_read_resource(dev, 0, &pcie->pads); 491 if (err < 0) { 492 pr_err("resource \"pads\" not found"); 493 return err; 494 } 495 496 err = dev_read_resource(dev, 1, &pcie->afi); 497 if (err < 0) { 498 pr_err("resource \"afi\" not found"); 499 return err; 500 } 501 502 err = dev_read_resource(dev, 2, &pcie->cs); 503 if (err < 0) { 504 pr_err("resource \"cs\" not found"); 505 return err; 506 } 507 508 err = tegra_pcie_board_init(); 509 if (err < 0) { 510 pr_err("tegra_pcie_board_init() failed: err=%d", err); 511 return err; 512 } 513 514 #ifndef CONFIG_TEGRA186 515 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); 516 if (pcie->phy) { 517 err = tegra_xusb_phy_prepare(pcie->phy); 518 if (err < 0) { 519 pr_err("failed to prepare PHY: %d", err); 520 return err; 521 } 522 } 523 #endif 524 525 dev_for_each_subnode(subnode, dev) { 526 unsigned int index = 0, num_lanes = 0; 527 struct tegra_pcie_port *port; 528 529 err = tegra_pcie_parse_port_info(subnode, &index, &num_lanes); 530 if (err < 0) { 531 pr_err("failed to obtain root port info"); 532 continue; 533 } 534 535 lanes |= num_lanes << (index << 3); 536 537 if (!ofnode_is_available(subnode)) 538 continue; 539 540 port = malloc(sizeof(*port)); 541 if (!port) 542 continue; 543 544 memset(port, 0, sizeof(*port)); 545 port->num_lanes = num_lanes; 546 port->index = index; 547 548 err = tegra_pcie_port_parse_dt(subnode, port); 549 if (err < 0) { 550 free(port); 551 continue; 552 } 553 554 list_add_tail(&port->list, &pcie->ports); 555 port->pcie = pcie; 556 } 557 558 err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id, 559 &pcie->xbar); 560 if (err < 0) { 561 pr_err("invalid lane configuration"); 562 return err; 563 } 564 565 return 0; 566 } 567 568 #ifdef CONFIG_TEGRA186 569 static int tegra_pcie_power_on(struct tegra_pcie *pcie) 570 { 571 int ret; 572 573 ret = power_domain_on(&pcie->pwrdom); 574 if (ret) { 575 pr_err("power_domain_on() failed: %d\n", ret); 576 return ret; 577 } 578 579 ret = clk_enable(&pcie->clk_afi); 580 if (ret) { 581 pr_err("clk_enable(afi) failed: %d\n", ret); 582 return ret; 583 } 584 585 ret = clk_enable(&pcie->clk_pex); 586 if (ret) { 587 pr_err("clk_enable(pex) failed: %d\n", ret); 588 return ret; 589 } 590 591 ret = reset_deassert(&pcie->reset_afi); 592 if (ret) { 593 pr_err("reset_deassert(afi) failed: %d\n", ret); 594 return ret; 595 } 596 597 ret = reset_deassert(&pcie->reset_pex); 598 if (ret) { 599 pr_err("reset_deassert(pex) failed: %d\n", ret); 600 return ret; 601 } 602 603 return 0; 604 } 605 #else 606 static int tegra_pcie_power_on(struct tegra_pcie *pcie) 607 { 608 const struct tegra_pcie_soc *soc = pcie->soc; 609 unsigned long value; 610 int err; 611 612 /* reset PCIEXCLK logic, AFI controller and PCIe controller */ 613 reset_set_enable(PERIPH_ID_PCIEXCLK, 1); 614 reset_set_enable(PERIPH_ID_AFI, 1); 615 reset_set_enable(PERIPH_ID_PCIE, 1); 616 617 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); 618 if (err < 0) { 619 pr_err("failed to power off PCIe partition: %d", err); 620 return err; 621 } 622 623 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, 624 PERIPH_ID_PCIE); 625 if (err < 0) { 626 pr_err("failed to power up PCIe partition: %d", err); 627 return err; 628 } 629 630 /* take AFI controller out of reset */ 631 reset_set_enable(PERIPH_ID_AFI, 0); 632 633 /* enable AFI clock */ 634 clock_enable(PERIPH_ID_AFI); 635 636 if (soc->has_cml_clk) { 637 /* enable CML clock */ 638 value = readl(NV_PA_CLK_RST_BASE + 0x48c); 639 value |= (1 << 0); 640 value &= ~(1 << 1); 641 writel(value, NV_PA_CLK_RST_BASE + 0x48c); 642 } 643 644 err = tegra_plle_enable(); 645 if (err < 0) { 646 pr_err("failed to enable PLLE: %d\n", err); 647 return err; 648 } 649 650 return 0; 651 } 652 653 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) 654 { 655 const struct tegra_pcie_soc *soc = pcie->soc; 656 unsigned long start = get_timer(0); 657 u32 value; 658 659 while (get_timer(start) < timeout) { 660 value = pads_readl(pcie, soc->pads_pll_ctl); 661 if (value & PADS_PLL_CTL_LOCKDET) 662 return 0; 663 } 664 665 return -ETIMEDOUT; 666 } 667 668 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) 669 { 670 const struct tegra_pcie_soc *soc = pcie->soc; 671 u32 value; 672 int err; 673 674 /* initialize internal PHY, enable up to 16 PCIe lanes */ 675 pads_writel(pcie, 0, PADS_CTL_SEL); 676 677 /* override IDDQ to 1 on all 4 lanes */ 678 value = pads_readl(pcie, PADS_CTL); 679 value |= PADS_CTL_IDDQ_1L; 680 pads_writel(pcie, value, PADS_CTL); 681 682 /* 683 * Set up PHY PLL inputs select PLLE output as refclock, set TX 684 * ref sel to div10 (not div5). 685 */ 686 value = pads_readl(pcie, soc->pads_pll_ctl); 687 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); 688 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; 689 pads_writel(pcie, value, soc->pads_pll_ctl); 690 691 /* reset PLL */ 692 value = pads_readl(pcie, soc->pads_pll_ctl); 693 value &= ~PADS_PLL_CTL_RST_B4SM; 694 pads_writel(pcie, value, soc->pads_pll_ctl); 695 696 udelay(20); 697 698 /* take PLL out of reset */ 699 value = pads_readl(pcie, soc->pads_pll_ctl); 700 value |= PADS_PLL_CTL_RST_B4SM; 701 pads_writel(pcie, value, soc->pads_pll_ctl); 702 703 /* wait for the PLL to lock */ 704 err = tegra_pcie_pll_wait(pcie, 500); 705 if (err < 0) { 706 pr_err("PLL failed to lock: %d", err); 707 return err; 708 } 709 710 /* turn off IDDQ override */ 711 value = pads_readl(pcie, PADS_CTL); 712 value &= ~PADS_CTL_IDDQ_1L; 713 pads_writel(pcie, value, PADS_CTL); 714 715 /* enable TX/RX data */ 716 value = pads_readl(pcie, PADS_CTL); 717 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; 718 pads_writel(pcie, value, PADS_CTL); 719 720 return 0; 721 } 722 #endif 723 724 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) 725 { 726 const struct tegra_pcie_soc *soc = pcie->soc; 727 struct tegra_pcie_port *port; 728 u32 value; 729 int err; 730 731 #ifdef CONFIG_TEGRA186 732 { 733 #else 734 if (pcie->phy) { 735 #endif 736 value = afi_readl(pcie, AFI_PLLE_CONTROL); 737 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 738 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 739 afi_writel(pcie, value, AFI_PLLE_CONTROL); 740 } 741 742 if (soc->has_pex_bias_ctrl) 743 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); 744 745 value = afi_readl(pcie, AFI_PCIE_CONFIG); 746 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 747 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar; 748 749 list_for_each_entry(port, &pcie->ports, list) 750 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); 751 752 afi_writel(pcie, value, AFI_PCIE_CONFIG); 753 754 value = afi_readl(pcie, AFI_FUSE); 755 756 if (soc->has_gen2) 757 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 758 else 759 value |= AFI_FUSE_PCIE_T0_GEN2_DIS; 760 761 afi_writel(pcie, value, AFI_FUSE); 762 763 #ifndef CONFIG_TEGRA186 764 if (pcie->phy) 765 err = tegra_xusb_phy_enable(pcie->phy); 766 else 767 err = tegra_pcie_phy_enable(pcie); 768 769 if (err < 0) { 770 pr_err("failed to power on PHY: %d\n", err); 771 return err; 772 } 773 #endif 774 775 /* take the PCIEXCLK logic out of reset */ 776 #ifdef CONFIG_TEGRA186 777 err = reset_deassert(&pcie->reset_pcie_x); 778 if (err) { 779 pr_err("reset_deassert(pcie_x) failed: %d\n", err); 780 return err; 781 } 782 #else 783 reset_set_enable(PERIPH_ID_PCIEXCLK, 0); 784 #endif 785 786 /* finally enable PCIe */ 787 value = afi_readl(pcie, AFI_CONFIGURATION); 788 value |= AFI_CONFIGURATION_EN_FPCI; 789 afi_writel(pcie, value, AFI_CONFIGURATION); 790 791 /* disable all interrupts */ 792 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE); 793 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE); 794 afi_writel(pcie, 0, AFI_INTR_MASK); 795 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); 796 797 return 0; 798 } 799 800 static int tegra_pcie_setup_translations(struct udevice *bus) 801 { 802 struct tegra_pcie *pcie = dev_get_priv(bus); 803 unsigned long fpci, axi, size; 804 struct pci_region *io, *mem, *pref; 805 int count; 806 807 /* BAR 0: type 1 extended configuration space */ 808 fpci = 0xfe100000; 809 size = resource_size(&pcie->cs); 810 axi = pcie->cs.start; 811 812 afi_writel(pcie, axi, AFI_AXI_BAR0_START); 813 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); 814 afi_writel(pcie, fpci, AFI_FPCI_BAR0); 815 816 count = pci_get_regions(bus, &io, &mem, &pref); 817 if (count != 3) 818 return -EINVAL; 819 820 /* BAR 1: downstream I/O */ 821 fpci = 0xfdfc0000; 822 size = io->size; 823 axi = io->phys_start; 824 825 afi_writel(pcie, axi, AFI_AXI_BAR1_START); 826 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); 827 afi_writel(pcie, fpci, AFI_FPCI_BAR1); 828 829 /* BAR 2: prefetchable memory */ 830 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; 831 size = pref->size; 832 axi = pref->phys_start; 833 834 afi_writel(pcie, axi, AFI_AXI_BAR2_START); 835 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); 836 afi_writel(pcie, fpci, AFI_FPCI_BAR2); 837 838 /* BAR 3: non-prefetchable memory */ 839 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; 840 size = mem->size; 841 axi = mem->phys_start; 842 843 afi_writel(pcie, axi, AFI_AXI_BAR3_START); 844 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); 845 afi_writel(pcie, fpci, AFI_FPCI_BAR3); 846 847 /* NULL out the remaining BARs as they are not used */ 848 afi_writel(pcie, 0, AFI_AXI_BAR4_START); 849 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); 850 afi_writel(pcie, 0, AFI_FPCI_BAR4); 851 852 afi_writel(pcie, 0, AFI_AXI_BAR5_START); 853 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); 854 afi_writel(pcie, 0, AFI_FPCI_BAR5); 855 856 /* map all upstream transactions as uncached */ 857 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST); 858 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); 859 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); 860 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); 861 862 /* MSI translations are setup only when needed */ 863 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); 864 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 865 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); 866 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 867 868 return 0; 869 } 870 871 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) 872 { 873 unsigned long ret = 0; 874 875 switch (port->index) { 876 case 0: 877 ret = AFI_PEX0_CTRL; 878 break; 879 880 case 1: 881 ret = AFI_PEX1_CTRL; 882 break; 883 884 case 2: 885 ret = port->pcie->soc->afi_pex2_ctrl; 886 break; 887 } 888 889 return ret; 890 } 891 892 void tegra_pcie_port_reset(struct tegra_pcie_port *port) 893 { 894 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 895 unsigned long value; 896 897 /* pulse reset signel */ 898 value = afi_readl(port->pcie, ctrl); 899 value &= ~AFI_PEX_CTRL_RST; 900 afi_writel(port->pcie, value, ctrl); 901 902 udelay(2000); 903 904 value = afi_readl(port->pcie, ctrl); 905 value |= AFI_PEX_CTRL_RST; 906 afi_writel(port->pcie, value, ctrl); 907 } 908 909 int tegra_pcie_port_index_of_port(struct tegra_pcie_port *port) 910 { 911 return port->index; 912 } 913 914 void __weak tegra_pcie_board_port_reset(struct tegra_pcie_port *port) 915 { 916 tegra_pcie_port_reset(port); 917 } 918 919 static void tegra_pcie_port_enable(struct tegra_pcie_port *port) 920 { 921 struct tegra_pcie *pcie = port->pcie; 922 const struct tegra_pcie_soc *soc = pcie->soc; 923 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 924 unsigned long value; 925 926 /* enable reference clock */ 927 value = afi_readl(pcie, ctrl); 928 value |= AFI_PEX_CTRL_REFCLK_EN; 929 930 if (pcie->soc->has_pex_clkreq_en) 931 value |= AFI_PEX_CTRL_CLKREQ_EN; 932 933 value |= AFI_PEX_CTRL_OVERRIDE_EN; 934 935 afi_writel(pcie, value, ctrl); 936 937 tegra_pcie_board_port_reset(port); 938 939 if (soc->force_pca_enable) { 940 value = rp_readl(port, RP_VEND_CTL2); 941 value |= RP_VEND_CTL2_PCA_ENABLE; 942 rp_writel(port, value, RP_VEND_CTL2); 943 } 944 945 /* configure the reference clock driver */ 946 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); 947 if (soc->num_ports > 2) 948 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); 949 } 950 951 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) 952 { 953 unsigned int retries = 3; 954 unsigned long value; 955 956 value = rp_readl(port, RP_PRIV_MISC); 957 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 958 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 959 rp_writel(port, value, RP_PRIV_MISC); 960 961 do { 962 unsigned int timeout = 200; 963 964 do { 965 value = rp_readl(port, RP_VEND_XP); 966 if (value & RP_VEND_XP_DL_UP) 967 break; 968 969 udelay(2000); 970 } while (--timeout); 971 972 if (!timeout) { 973 debug("link %u down, retrying\n", port->index); 974 goto retry; 975 } 976 977 timeout = 200; 978 979 do { 980 value = rp_readl(port, RP_LINK_CONTROL_STATUS); 981 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 982 return true; 983 984 udelay(2000); 985 } while (--timeout); 986 987 retry: 988 tegra_pcie_board_port_reset(port); 989 } while (--retries); 990 991 return false; 992 } 993 994 static void tegra_pcie_port_disable(struct tegra_pcie_port *port) 995 { 996 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 997 unsigned long value; 998 999 /* assert port reset */ 1000 value = afi_readl(port->pcie, ctrl); 1001 value &= ~AFI_PEX_CTRL_RST; 1002 afi_writel(port->pcie, value, ctrl); 1003 1004 /* disable reference clock */ 1005 value = afi_readl(port->pcie, ctrl); 1006 value &= ~AFI_PEX_CTRL_REFCLK_EN; 1007 afi_writel(port->pcie, value, ctrl); 1008 } 1009 1010 static void tegra_pcie_port_free(struct tegra_pcie_port *port) 1011 { 1012 list_del(&port->list); 1013 free(port); 1014 } 1015 1016 static int tegra_pcie_enable(struct tegra_pcie *pcie) 1017 { 1018 struct tegra_pcie_port *port, *tmp; 1019 1020 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 1021 debug("probing port %u, using %u lanes\n", port->index, 1022 port->num_lanes); 1023 1024 tegra_pcie_port_enable(port); 1025 1026 if (tegra_pcie_port_check_link(port)) 1027 continue; 1028 1029 debug("link %u down, ignoring\n", port->index); 1030 1031 tegra_pcie_port_disable(port); 1032 tegra_pcie_port_free(port); 1033 } 1034 1035 return 0; 1036 } 1037 1038 static const struct tegra_pcie_soc pci_tegra_soc[] = { 1039 [TEGRA20_PCIE] = { 1040 .num_ports = 2, 1041 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, 1042 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, 1043 .pads_refclk_cfg0 = 0xfa5cfa5c, 1044 .has_pex_clkreq_en = false, 1045 .has_pex_bias_ctrl = false, 1046 .has_cml_clk = false, 1047 .has_gen2 = false, 1048 }, 1049 [TEGRA30_PCIE] = { 1050 .num_ports = 3, 1051 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1052 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1053 .afi_pex2_ctrl = AFI_PEX2_CTRL, 1054 .pads_refclk_cfg0 = 0xfa5cfa5c, 1055 .pads_refclk_cfg1 = 0xfa5cfa5c, 1056 .has_pex_clkreq_en = true, 1057 .has_pex_bias_ctrl = true, 1058 .has_cml_clk = true, 1059 .has_gen2 = false, 1060 }, 1061 [TEGRA124_PCIE] = { 1062 .num_ports = 2, 1063 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1064 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1065 .pads_refclk_cfg0 = 0x44ac44ac, 1066 .has_pex_clkreq_en = true, 1067 .has_pex_bias_ctrl = true, 1068 .has_cml_clk = true, 1069 .has_gen2 = true, 1070 }, 1071 [TEGRA210_PCIE] = { 1072 .num_ports = 2, 1073 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1074 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1075 .pads_refclk_cfg0 = 0x90b890b8, 1076 .has_pex_clkreq_en = true, 1077 .has_pex_bias_ctrl = true, 1078 .has_cml_clk = true, 1079 .has_gen2 = true, 1080 .force_pca_enable = true, 1081 }, 1082 [TEGRA186_PCIE] = { 1083 .num_ports = 3, 1084 .afi_pex2_ctrl = AFI_PEX2_CTRL_T186, 1085 .pads_refclk_cfg0 = 0x80b880b8, 1086 .pads_refclk_cfg1 = 0x000480b8, 1087 .has_pex_clkreq_en = true, 1088 .has_pex_bias_ctrl = true, 1089 .has_gen2 = true, 1090 }, 1091 }; 1092 1093 static int pci_tegra_ofdata_to_platdata(struct udevice *dev) 1094 { 1095 struct tegra_pcie *pcie = dev_get_priv(dev); 1096 enum tegra_pci_id id; 1097 1098 id = dev_get_driver_data(dev); 1099 pcie->soc = &pci_tegra_soc[id]; 1100 1101 INIT_LIST_HEAD(&pcie->ports); 1102 1103 if (tegra_pcie_parse_dt(dev, id, pcie)) 1104 return -EINVAL; 1105 1106 return 0; 1107 } 1108 1109 static int pci_tegra_probe(struct udevice *dev) 1110 { 1111 struct tegra_pcie *pcie = dev_get_priv(dev); 1112 int err; 1113 1114 #ifdef CONFIG_TEGRA186 1115 err = clk_get_by_name(dev, "afi", &pcie->clk_afi); 1116 if (err) { 1117 debug("clk_get_by_name(afi) failed: %d\n", err); 1118 return err; 1119 } 1120 1121 err = clk_get_by_name(dev, "pex", &pcie->clk_pex); 1122 if (err) { 1123 debug("clk_get_by_name(pex) failed: %d\n", err); 1124 return err; 1125 } 1126 1127 err = reset_get_by_name(dev, "afi", &pcie->reset_afi); 1128 if (err) { 1129 debug("reset_get_by_name(afi) failed: %d\n", err); 1130 return err; 1131 } 1132 1133 err = reset_get_by_name(dev, "pex", &pcie->reset_pex); 1134 if (err) { 1135 debug("reset_get_by_name(pex) failed: %d\n", err); 1136 return err; 1137 } 1138 1139 err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x); 1140 if (err) { 1141 debug("reset_get_by_name(pcie_x) failed: %d\n", err); 1142 return err; 1143 } 1144 1145 err = power_domain_get(dev, &pcie->pwrdom); 1146 if (err) { 1147 debug("power_domain_get() failed: %d\n", err); 1148 return err; 1149 } 1150 #endif 1151 1152 err = tegra_pcie_power_on(pcie); 1153 if (err < 0) { 1154 pr_err("failed to power on"); 1155 return err; 1156 } 1157 1158 err = tegra_pcie_enable_controller(pcie); 1159 if (err < 0) { 1160 pr_err("failed to enable controller"); 1161 return err; 1162 } 1163 1164 err = tegra_pcie_setup_translations(dev); 1165 if (err < 0) { 1166 pr_err("failed to decode ranges"); 1167 return err; 1168 } 1169 1170 err = tegra_pcie_enable(pcie); 1171 if (err < 0) { 1172 pr_err("failed to enable PCIe"); 1173 return err; 1174 } 1175 1176 return 0; 1177 } 1178 1179 static const struct dm_pci_ops pci_tegra_ops = { 1180 .read_config = pci_tegra_read_config, 1181 .write_config = pci_tegra_write_config, 1182 }; 1183 1184 static const struct udevice_id pci_tegra_ids[] = { 1185 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE }, 1186 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE }, 1187 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE }, 1188 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE }, 1189 { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE }, 1190 { } 1191 }; 1192 1193 U_BOOT_DRIVER(pci_tegra) = { 1194 .name = "pci_tegra", 1195 .id = UCLASS_PCI, 1196 .of_match = pci_tegra_ids, 1197 .ops = &pci_tegra_ops, 1198 .ofdata_to_platdata = pci_tegra_ofdata_to_platdata, 1199 .probe = pci_tegra_probe, 1200 .priv_auto_alloc_size = sizeof(struct tegra_pcie), 1201 }; 1202
