1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 4 * Toradex, Inc. 5 * 6 * Authors: Stefan Agner 7 * Sanchayan Maity 8 */ 9 10 #ifndef __ASM_ARCH_VF610_DDRMC_H 11 #define __ASM_ARCH_VF610_DDRMC_H 12 13 struct ddr3_jedec_timings { 14 u8 tinit; 15 u32 trst_pwron; 16 u32 cke_inactive; 17 u8 wrlat; 18 u8 caslat_lin; 19 u8 trc; 20 u8 trrd; 21 u8 tccd; 22 u8 tbst_int_interval; 23 u8 tfaw; 24 u8 trp; 25 u8 twtr; 26 u8 tras_min; 27 u8 tmrd; 28 u8 trtp; 29 u32 tras_max; 30 u8 tmod; 31 u8 tckesr; 32 u8 tcke; 33 u8 trcd_int; 34 u8 tras_lockout; 35 u8 tdal; 36 u8 bstlen; 37 u16 tdll; 38 u8 trp_ab; 39 u16 tref; 40 u8 trfc; 41 u16 tref_int; 42 u8 tpdex; 43 u8 txpdll; 44 u8 txsnr; 45 u16 txsr; 46 u8 cksrx; 47 u8 cksre; 48 u8 freq_chg_en; 49 u16 zqcl; 50 u16 zqinit; 51 u8 zqcs; 52 u8 ref_per_zq; 53 u8 zqcs_rotate; 54 u8 aprebit; 55 u8 cmd_age_cnt; 56 u8 age_cnt; 57 u8 q_fullness; 58 u8 odt_rd_mapcs0; 59 u8 odt_wr_mapcs0; 60 u8 wlmrd; 61 u8 wldqsen; 62 }; 63 64 struct ddrmc_cr_setting { 65 u32 setting; 66 int cr_rnum; /* CR register ; -1 for last entry */ 67 }; 68 69 struct ddrmc_phy_setting { 70 u32 setting; 71 int phy_rnum; /* PHY register ; -1 for last entry */ 72 }; 73 74 void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count); 75 void ddrmc_phy_init(void); 76 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, 77 struct ddrmc_cr_setting *board_cr_settings, 78 struct ddrmc_phy_setting *board_phy_settings, 79 int col_diff, int row_diff); 80 81 #endif 82
