1 /****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 */ 20 /*! 21 ************************************************************************** 22 * \file ih264d_utils.c 23 * 24 * \brief 25 * Contains routines that handle of start and end of pic processing 26 * 27 * \date 28 * 19/12/2002 29 * 30 * \author AI 31 ************************************************************************** 32 */ 33 34 #include <string.h> 35 #include "ih264_typedefs.h" 36 #include "ithread.h" 37 #include "ih264d_deblocking.h" 38 #include "ih264d_parse_slice.h" 39 #include "ih264d_parse_cavlc.h" 40 #include "ih264d_dpb_manager.h" 41 #include "ih264d_defs.h" 42 #include "ih264d_structs.h" 43 #include "ih264d_mem_request.h" 44 #include "ih264_typedefs.h" 45 #include "ih264_macros.h" 46 #include "ih264_platform_macros.h" 47 #include "ih264d_tables.h" 48 #include "ih264d_debug.h" 49 #include "ih264d_mb_utils.h" 50 #include "ih264d_error_handler.h" 51 #include "ih264d_dpb_manager.h" 52 #include "ih264d_utils.h" 53 #include "ih264d_defs.h" 54 #include "ih264d_tables.h" 55 #include "ih264d_inter_pred.h" 56 #include "ih264d_dpb_manager.h" 57 #include "iv.h" 58 #include "ivd.h" 59 #include "ih264d_format_conv.h" 60 #include "ih264_error.h" 61 #include "ih264_disp_mgr.h" 62 #include "ih264_buf_mgr.h" 63 #include "ih264d_utils.h" 64 65 /*! 66 ************************************************************************** 67 * \if Function name : ih264d_is_end_of_pic \endif 68 * 69 * \brief 70 * Determines whether current slice is first slice of a new picture as 71 * defined in 7.4.1.2.4 of 14496-10. 72 * 73 * \return 74 * Return 1 if current slice is first slice of a new picture 75 * Otherwise it returns 0 76 ************************************************************************** 77 */ 78 UWORD8 ih264d_is_end_of_pic(UWORD16 u2_frame_num, 79 UWORD8 u1_nal_ref_idc, 80 pocstruct_t *ps_cur_poc, 81 pocstruct_t *ps_prev_poc, 82 dec_slice_params_t * ps_prev_slice, /*!< Previous slice parameters*/ 83 UWORD8 u1_pic_order_cnt_type, 84 UWORD8 u1_nal_unit_type, 85 UWORD32 u4_idr_pic_id, 86 UWORD8 u1_field_pic_flag, 87 UWORD8 u1_bottom_field_flag) 88 { 89 WORD8 i1_is_end_of_pic; 90 WORD8 a, b, c, d, e, f, g, h; 91 92 a = b = c = d = e = f = g = h = 0; 93 a = (ps_prev_slice->u2_frame_num != u2_frame_num); 94 b = (ps_prev_slice->u1_field_pic_flag != u1_field_pic_flag); 95 if(u1_field_pic_flag && ps_prev_slice->u1_field_pic_flag) 96 c = (u1_bottom_field_flag != ps_prev_slice->u1_bottom_field_flag); 97 d = 98 (u1_nal_ref_idc == 0 && ps_prev_slice->u1_nal_ref_idc != 0) 99 || (u1_nal_ref_idc != 0 100 && ps_prev_slice->u1_nal_ref_idc 101 == 0); 102 if(!a) 103 { 104 if((u1_pic_order_cnt_type == 0) 105 && (ps_prev_slice->u1_pic_order_cnt_type == 0)) 106 { 107 e = 108 ((ps_cur_poc->i4_pic_order_cnt_lsb 109 != ps_prev_poc->i4_pic_order_cnt_lsb) 110 || (ps_cur_poc->i4_delta_pic_order_cnt_bottom 111 != ps_prev_poc->i4_delta_pic_order_cnt_bottom)); 112 } 113 114 if((u1_pic_order_cnt_type == 1) 115 && (ps_prev_slice->u1_pic_order_cnt_type == 1)) 116 { 117 f = 118 ((ps_cur_poc->i4_delta_pic_order_cnt[0] 119 != ps_prev_poc->i4_delta_pic_order_cnt[0]) 120 || (ps_cur_poc->i4_delta_pic_order_cnt[1] 121 != ps_prev_poc->i4_delta_pic_order_cnt[1])); 122 } 123 } 124 125 if((u1_nal_unit_type == IDR_SLICE_NAL) 126 && (ps_prev_slice->u1_nal_unit_type == IDR_SLICE_NAL)) 127 { 128 g = (u4_idr_pic_id != ps_prev_slice->u4_idr_pic_id); 129 } 130 131 if((u1_nal_unit_type == IDR_SLICE_NAL) 132 && (ps_prev_slice->u1_nal_unit_type != IDR_SLICE_NAL)) 133 { 134 h = 1; 135 } 136 i1_is_end_of_pic = a + b + c + d + e + f + g + h; 137 return (i1_is_end_of_pic); 138 } 139 140 /*! 141 ************************************************************************** 142 * \if Function name : ih264d_decode_pic_order_cnt \endif 143 * 144 * \brief 145 * Calculates picture order count of picture. 146 * 147 * \return 148 * Returns the pic order count of the picture to which current 149 * Slice belongs. 150 * 151 ************************************************************************** 152 */ 153 WORD32 ih264d_decode_pic_order_cnt(UWORD8 u1_is_idr_slice, 154 UWORD32 u2_frame_num, 155 pocstruct_t *ps_prev_poc, 156 pocstruct_t *ps_cur_poc, 157 dec_slice_params_t *ps_cur_slice, /*!< Pointer to current slice Params*/ 158 dec_pic_params_t * ps_pps, 159 UWORD8 u1_nal_ref_idc, 160 UWORD8 u1_bottom_field_flag, 161 UWORD8 u1_field_pic_flag, 162 WORD32 *pi4_poc) 163 { 164 WORD16 i1_pic_msb; 165 WORD32 i4_top_field_order_cnt = 0, i4_bottom_field_order_cnt = 0; 166 dec_seq_params_t *ps_seq = ps_pps->ps_sps; 167 WORD32 i4_prev_frame_num_ofst; 168 169 switch(ps_seq->u1_pic_order_cnt_type) 170 { 171 case 0: 172 /* POC TYPE 0 */ 173 if(u1_is_idr_slice) 174 { 175 ps_prev_poc->i4_pic_order_cnt_msb = 0; 176 ps_prev_poc->i4_pic_order_cnt_lsb = 0; 177 } 178 if(ps_prev_poc->u1_mmco_equalto5) 179 { 180 if(ps_prev_poc->u1_bot_field != 1) 181 { 182 ps_prev_poc->i4_pic_order_cnt_msb = 0; 183 ps_prev_poc->i4_pic_order_cnt_lsb = 184 ps_prev_poc->i4_top_field_order_count; 185 } 186 else 187 { 188 ps_prev_poc->i4_pic_order_cnt_msb = 0; 189 ps_prev_poc->i4_pic_order_cnt_lsb = 0; 190 } 191 } 192 193 if((ps_cur_poc->i4_pic_order_cnt_lsb 194 < ps_prev_poc->i4_pic_order_cnt_lsb) 195 && ((ps_prev_poc->i4_pic_order_cnt_lsb 196 - ps_cur_poc->i4_pic_order_cnt_lsb) 197 >= (ps_seq->i4_max_pic_order_cntLsb 198 >> 1))) 199 { 200 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb 201 + ps_seq->i4_max_pic_order_cntLsb; 202 } 203 else if((ps_cur_poc->i4_pic_order_cnt_lsb 204 > ps_prev_poc->i4_pic_order_cnt_lsb) 205 && ((ps_cur_poc->i4_pic_order_cnt_lsb 206 - ps_prev_poc->i4_pic_order_cnt_lsb) 207 >= (ps_seq->i4_max_pic_order_cntLsb 208 >> 1))) 209 { 210 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb 211 - ps_seq->i4_max_pic_order_cntLsb; 212 } 213 else 214 { 215 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb; 216 } 217 218 if(!u1_field_pic_flag || !u1_bottom_field_flag) 219 i4_top_field_order_cnt = i1_pic_msb 220 + ps_cur_poc->i4_pic_order_cnt_lsb; 221 222 if(!u1_field_pic_flag) 223 { 224 i4_bottom_field_order_cnt = i4_top_field_order_cnt 225 + ps_cur_poc->i4_delta_pic_order_cnt_bottom; 226 } 227 else if(u1_bottom_field_flag) 228 { 229 i4_bottom_field_order_cnt = i1_pic_msb 230 + ps_cur_poc->i4_pic_order_cnt_lsb; 231 } 232 ps_cur_poc->i4_pic_order_cnt_msb = i1_pic_msb; 233 break; 234 235 case 1: 236 { 237 /* POC TYPE 1 */ 238 UWORD8 i; 239 WORD32 prev_frame_num; 240 WORD32 frame_num_ofst; 241 WORD32 abs_frm_num; 242 WORD32 poc_cycle_cnt, frame_num_in_poc_cycle; 243 WORD64 i8_expected_delta_poc_cycle; 244 WORD32 expected_poc; 245 WORD64 i8_result; 246 247 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num; 248 if(!u1_is_idr_slice) 249 { 250 if(ps_cur_slice->u1_mmco_equalto5) 251 { 252 prev_frame_num = 0; 253 i4_prev_frame_num_ofst = 0; 254 } 255 else 256 { 257 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst; 258 } 259 } 260 else 261 i4_prev_frame_num_ofst = 0; 262 263 /* 1. Derivation for FrameNumOffset */ 264 if(u1_is_idr_slice) 265 { 266 frame_num_ofst = 0; 267 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 268 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 269 } 270 else if(prev_frame_num > ((WORD32)u2_frame_num)) 271 { 272 frame_num_ofst = i4_prev_frame_num_ofst 273 + (WORD32)ps_seq->u2_u4_max_pic_num_minus1 + 1; 274 } 275 else 276 frame_num_ofst = i4_prev_frame_num_ofst; 277 278 /* 2. Derivation for absFrameNum */ 279 if(0 != ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle) 280 abs_frm_num = frame_num_ofst + (WORD32)u2_frame_num; 281 else 282 abs_frm_num = 0; 283 if((u1_nal_ref_idc == 0) && (abs_frm_num > 0)) 284 abs_frm_num = abs_frm_num - 1; 285 286 /* 4. expectedDeltaPerPicOrderCntCycle is derived as */ 287 i8_expected_delta_poc_cycle = 0; 288 for(i = 0; i < ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle; 289 i++) 290 { 291 i8_expected_delta_poc_cycle += 292 ps_seq->i4_ofst_for_ref_frame[i]; 293 } 294 295 /* 3. When absFrameNum > 0, picOrderCntCycleCnt and 296 frame_num_in_poc_cycle are derived as : */ 297 /* 5. expectedPicOrderCnt is derived as : */ 298 if(abs_frm_num > 0) 299 { 300 poc_cycle_cnt = 301 DIV((abs_frm_num - 1), 302 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle); 303 frame_num_in_poc_cycle = 304 MOD((abs_frm_num - 1), 305 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle); 306 307 i8_result = poc_cycle_cnt 308 * i8_expected_delta_poc_cycle; 309 310 for(i = 0; i <= frame_num_in_poc_cycle; i++) 311 { 312 i8_result = i8_result 313 + ps_seq->i4_ofst_for_ref_frame[i]; 314 } 315 316 if(IS_OUT_OF_RANGE_S32(i8_result)) 317 return ERROR_INV_POC; 318 319 expected_poc = (WORD32)i8_result; 320 321 } 322 else 323 expected_poc = 0; 324 325 if(u1_nal_ref_idc == 0) 326 { 327 i8_result = expected_poc 328 + ps_seq->i4_ofst_for_non_ref_pic; 329 330 if(IS_OUT_OF_RANGE_S32(i8_result)) 331 return ERROR_INV_POC; 332 333 expected_poc = (WORD32)i8_result; 334 } 335 336 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */ 337 if(!u1_field_pic_flag) 338 { 339 i8_result = expected_poc 340 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 341 342 if(IS_OUT_OF_RANGE_S32(i8_result)) 343 return ERROR_INV_POC; 344 i4_top_field_order_cnt = (WORD32)i8_result; 345 346 i8_result = i4_top_field_order_cnt 347 + ps_seq->i4_ofst_for_top_to_bottom_field 348 + ps_cur_poc->i4_delta_pic_order_cnt[1]; 349 350 if(IS_OUT_OF_RANGE_S32(i8_result)) 351 return ERROR_INV_POC; 352 i4_bottom_field_order_cnt = (WORD32)i8_result; 353 } 354 else if(!u1_bottom_field_flag) 355 { 356 i8_result = expected_poc 357 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 358 359 if(IS_OUT_OF_RANGE_S32(i8_result)) 360 return ERROR_INV_POC; 361 i4_top_field_order_cnt = (WORD32)i8_result; 362 } 363 else 364 { 365 i8_result = expected_poc 366 + ps_seq->i4_ofst_for_top_to_bottom_field 367 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 368 369 if(IS_OUT_OF_RANGE_S32(i8_result)) 370 return ERROR_INV_POC; 371 i4_bottom_field_order_cnt = (WORD32)i8_result; 372 } 373 /* Copy the current POC info into Previous POC structure */ 374 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst; 375 } 376 377 break; 378 case 2: 379 { 380 /* POC TYPE 2 */ 381 WORD32 prev_frame_num; 382 WORD32 frame_num_ofst; 383 WORD32 tmp_poc; 384 385 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num; 386 if(!u1_is_idr_slice) 387 { 388 if(ps_cur_slice->u1_mmco_equalto5) 389 { 390 prev_frame_num = 0; 391 i4_prev_frame_num_ofst = 0; 392 } 393 else 394 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst; 395 } 396 else 397 i4_prev_frame_num_ofst = 0; 398 399 /* 1. Derivation for FrameNumOffset */ 400 if(u1_is_idr_slice) 401 { 402 frame_num_ofst = 0; 403 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 404 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 405 } 406 else if(prev_frame_num > ((WORD32)u2_frame_num)) 407 { 408 frame_num_ofst = i4_prev_frame_num_ofst 409 + (WORD32)ps_seq->u2_u4_max_pic_num_minus1 + 1; 410 } 411 else 412 frame_num_ofst = i4_prev_frame_num_ofst; 413 414 /* 2. Derivation for tempPicOrderCnt */ 415 if(u1_is_idr_slice) 416 tmp_poc = 0; 417 else if(u1_nal_ref_idc == 0) 418 tmp_poc = ((frame_num_ofst + (WORD32)u2_frame_num) << 1) 419 - 1; 420 else 421 tmp_poc = ((frame_num_ofst + (WORD32)u2_frame_num) << 1); 422 423 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */ 424 if(!u1_field_pic_flag) 425 { 426 i4_top_field_order_cnt = tmp_poc; 427 i4_bottom_field_order_cnt = tmp_poc; 428 } 429 else if(!u1_bottom_field_flag) 430 i4_top_field_order_cnt = tmp_poc; 431 else 432 i4_bottom_field_order_cnt = tmp_poc; 433 434 /* Copy the current POC info into Previous POC structure */ 435 ps_prev_poc->i4_prev_frame_num_ofst = frame_num_ofst; 436 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst; 437 } 438 break; 439 default: 440 return ERROR_INV_POC_TYPE_T; 441 break; 442 } 443 444 if(!u1_field_pic_flag) // or a complementary field pair 445 { 446 *pi4_poc = MIN(i4_top_field_order_cnt, i4_bottom_field_order_cnt); 447 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt; 448 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt; 449 } 450 else if(!u1_bottom_field_flag) 451 { 452 *pi4_poc = i4_top_field_order_cnt; 453 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt; 454 } 455 else 456 { 457 *pi4_poc = i4_bottom_field_order_cnt; 458 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt; 459 } 460 461 ps_pps->i4_avg_poc = *pi4_poc; 462 463 return OK; 464 } 465 466 /*! 467 ************************************************************************** 468 * \if Function name : ih264d_end_of_pic_processing \endif 469 * 470 * \brief 471 * Performs the end of picture processing. 472 * 473 * It performs deblocking on the current picture and sets the i4_status of 474 * current picture as decoded. 475 * 476 * \return 477 * 0 on Success and Error code otherwise. 478 ************************************************************************** 479 */ 480 WORD32 ih264d_end_of_pic_processing(dec_struct_t *ps_dec) 481 { 482 UWORD8 u1_pic_type, u1_nal_ref_idc; 483 dec_slice_params_t *ps_cur_slice = ps_dec->ps_cur_slice; 484 485 /* If nal_ref_idc is equal to 0 for one slice or slice data partition NAL 486 unit of a particular picture, it shall be equal to 0 for all slice and 487 slice data partition NAL units of the picture. nal_ref_idc greater 488 than 0 indicates that the content of the NAL unit belongs to a decoded 489 picture that is stored and marked for use as a reference picture in the 490 decoded picture buffer. */ 491 492 /* 1. Do MMCO 493 2. Add Cur Pic to list of reference pics. 494 */ 495 496 /* Call MMCO */ 497 u1_pic_type = 0; 498 u1_nal_ref_idc = ps_cur_slice->u1_nal_ref_idc; 499 500 if(u1_nal_ref_idc) 501 { 502 if(ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL) 503 { 504 if(ps_dec->ps_dpb_cmds->u1_long_term_reference_flag == 0) 505 { 506 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr); 507 /* ignore DPB errors */ 508 ih264d_insert_st_node(ps_dec->ps_dpb_mgr, 509 ps_dec->ps_cur_pic, 510 ps_dec->u1_pic_buf_id, 511 ps_cur_slice->u2_frame_num); 512 } 513 else 514 { 515 /* Equivalent of inserting a pic directly as longterm Pic */ 516 517 { 518 /* ignore DPB errors */ 519 ih264d_insert_st_node(ps_dec->ps_dpb_mgr, 520 ps_dec->ps_cur_pic, 521 ps_dec->u1_pic_buf_id, 522 ps_cur_slice->u2_frame_num); 523 524 /* Set longTermIdx = 0, MaxLongTermFrameIdx = 0 */ 525 ih264d_delete_st_node_or_make_lt( 526 ps_dec->ps_dpb_mgr, 527 ps_cur_slice->u2_frame_num, 0, 528 ps_cur_slice->u1_field_pic_flag); 529 530 ps_dec->ps_dpb_mgr->u1_max_lt_pic_idx_plus1 = 1; 531 } 532 } 533 } 534 else 535 { 536 537 { 538 UWORD16 u2_pic_num = ps_cur_slice->u2_frame_num; 539 540 /* ignore DPB errors */ 541 ih264d_do_mmco_buffer(ps_dec->ps_dpb_cmds, ps_dec->ps_dpb_mgr, 542 ps_dec->ps_cur_sps->u1_num_ref_frames, u2_pic_num, 543 (ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1), 544 ps_dec->u1_nal_unit_type, ps_dec->ps_cur_pic, 545 ps_dec->u1_pic_buf_id, 546 ps_cur_slice->u1_field_pic_flag, 547 ps_dec->e_dec_status); 548 549 550 } 551 } 552 ih264d_update_default_index_list(ps_dec->ps_dpb_mgr); 553 } 554 555 if(ps_cur_slice->u1_field_pic_flag) 556 { 557 if(ps_cur_slice->u1_bottom_field_flag) 558 { 559 if(u1_nal_ref_idc) 560 u1_pic_type = u1_pic_type | BOT_REF; 561 u1_pic_type = u1_pic_type | BOT_FLD; 562 } 563 else 564 { 565 if(u1_nal_ref_idc) 566 u1_pic_type = u1_pic_type | TOP_REF; 567 u1_pic_type = u1_pic_type | TOP_FLD; 568 } 569 } 570 else 571 u1_pic_type = TOP_REF | BOT_REF; 572 ps_dec->ps_cur_pic->u1_pic_type |= u1_pic_type; 573 574 575 if(ps_cur_slice->u1_field_pic_flag) 576 { 577 H264_DEC_DEBUG_PRINT("Toggling secondField\n"); 578 ps_dec->u1_second_field = 1 - ps_dec->u1_second_field; 579 } 580 581 return OK; 582 } 583 584 /*****************************************************************************/ 585 /* */ 586 /* Function Name : init_dpb_size */ 587 /* */ 588 /* Description : This function calculates the DBP i4_size in frames */ 589 /* Inputs : ps_seq - current sequence params */ 590 /* */ 591 /* Globals : None */ 592 /* */ 593 /* Outputs : None */ 594 /* */ 595 /* Returns : DPB in frames */ 596 /* */ 597 /* Issues : None */ 598 /* */ 599 /* Revision History: */ 600 /* */ 601 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 602 /* 28 04 2005 NS Draft */ 603 /* */ 604 /*****************************************************************************/ 605 WORD32 ih264d_get_dpb_size(dec_seq_params_t *ps_seq) 606 { 607 WORD32 i4_size; 608 UWORD8 u1_level_idc; 609 610 u1_level_idc = ps_seq->u1_level_idc; 611 612 switch(u1_level_idc) 613 { 614 case 10: 615 i4_size = 152064; 616 break; 617 case 11: 618 i4_size = 345600; 619 break; 620 case 12: 621 i4_size = 912384; 622 break; 623 case 13: 624 i4_size = 912384; 625 break; 626 case 20: 627 i4_size = 912384; 628 break; 629 case 21: 630 i4_size = 1824768; 631 break; 632 case 22: 633 i4_size = 3110400; 634 break; 635 case 30: 636 i4_size = 3110400; 637 break; 638 case 31: 639 i4_size = 6912000; 640 break; 641 case 32: 642 i4_size = 7864320; 643 break; 644 case 40: 645 i4_size = 12582912; 646 break; 647 case 41: 648 i4_size = 12582912; 649 break; 650 case 42: 651 i4_size = 12582912; 652 break; 653 case 50: 654 i4_size = 42393600; 655 break; 656 case 51: 657 i4_size = 70778880; 658 break; 659 case 52: 660 i4_size = 70778880; 661 break; 662 default: 663 i4_size = 70778880; 664 break; 665 } 666 667 i4_size /= (ps_seq->u2_frm_wd_in_mbs * (ps_seq->u2_frm_ht_in_mbs << (1 - ps_seq->u1_frame_mbs_only_flag))); 668 i4_size /= 384; 669 i4_size = MIN(i4_size, 16); 670 i4_size = MAX(i4_size, 1); 671 return (i4_size); 672 } 673 674 /**************************************************************************/ 675 /* This function initialises the value of ps_dec->u1_recon_mb_grp */ 676 /* ps_dec->u1_recon_mb_grp must satisfy the following criteria */ 677 /* - multiple of 2 (required for N/2 parse-mvpred design) */ 678 /* - multiple of 4 (if it is not a frame_mbs_only sequence), */ 679 /* in this case N/2 itself needs to be even for mbpair processing */ 680 /* - lesser than ps_dec->u2_frm_wd_in_mbs/2 (at least 3 N-Chunks */ 681 /* should make a row to ensure proper MvTop transferring) */ 682 /**************************************************************************/ 683 WORD32 ih264d_init_dec_mb_grp(dec_struct_t *ps_dec) 684 { 685 dec_seq_params_t *ps_seq = ps_dec->ps_cur_sps; 686 UWORD8 u1_frm = ps_seq->u1_frame_mbs_only_flag; 687 688 ps_dec->u1_recon_mb_grp = ps_dec->u2_frm_wd_in_mbs << ps_seq->u1_mb_aff_flag; 689 690 ps_dec->u1_recon_mb_grp_pair = ps_dec->u1_recon_mb_grp >> 1; 691 692 if(!ps_dec->u1_recon_mb_grp) 693 { 694 return ERROR_MB_GROUP_ASSGN_T; 695 } 696 697 ps_dec->u4_num_mbs_prev_nmb = ps_dec->u1_recon_mb_grp; 698 699 return OK; 700 } 701 702 703 /*! 704 ************************************************************************** 705 * \if Function name : ih264d_init_pic \endif 706 * 707 * \brief 708 * Initializes the picture. 709 * 710 * \return 711 * 0 on Success and Error code otherwise 712 * 713 * \note 714 * This function is called when first slice of the 715 * NON -IDR picture is encountered. 716 ************************************************************************** 717 */ 718 WORD32 ih264d_init_pic(dec_struct_t *ps_dec, 719 UWORD16 u2_frame_num, 720 WORD32 i4_poc, 721 dec_pic_params_t *ps_pps) 722 { 723 dec_seq_params_t *ps_seq = ps_pps->ps_sps; 724 prev_seq_params_t * ps_prev_seq_params = &ps_dec->s_prev_seq_params; 725 WORD32 i4_pic_bufs; 726 WORD32 ret; 727 728 ps_dec->ps_cur_slice->u2_frame_num = u2_frame_num; 729 ps_dec->ps_cur_slice->i4_poc = i4_poc; 730 ps_dec->ps_cur_pps = ps_pps; 731 ps_dec->ps_cur_pps->pv_codec_handle = ps_dec; 732 733 ps_dec->ps_cur_sps = ps_seq; 734 ps_dec->ps_dpb_mgr->i4_max_frm_num = ps_seq->u2_u4_max_pic_num_minus1 735 + 1; 736 737 ps_dec->ps_dpb_mgr->u2_pic_ht = ps_dec->u2_pic_ht; 738 ps_dec->ps_dpb_mgr->u2_pic_wd = ps_dec->u2_pic_wd; 739 ps_dec->i4_pic_type = NA_SLICE; 740 ps_dec->i4_frametype = IV_NA_FRAME; 741 ps_dec->i4_content_type = IV_CONTENTTYPE_NA; 742 743 /*--------------------------------------------------------------------*/ 744 /* Get the value of MaxMbAddress and frmheight in Mbs */ 745 /*--------------------------------------------------------------------*/ 746 ps_seq->u2_max_mb_addr = 747 (ps_seq->u2_frm_wd_in_mbs 748 * (ps_dec->u2_pic_ht 749 >> (4 750 + ps_dec->ps_cur_slice->u1_field_pic_flag))) 751 - 1; 752 ps_dec->u2_frm_ht_in_mbs = (ps_dec->u2_pic_ht 753 >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag)); 754 755 /***************************************************************************/ 756 /* If change in Level or the required PicBuffers i4_size is more than the */ 757 /* current one FREE the current PicBuffers and allocate affresh */ 758 /***************************************************************************/ 759 if(!ps_dec->u1_init_dec_flag) 760 { 761 ps_dec->u1_max_dec_frame_buffering = ih264d_get_dpb_size(ps_seq); 762 763 ps_dec->i4_display_delay = ps_dec->u1_max_dec_frame_buffering; 764 if((1 == ps_seq->u1_vui_parameters_present_flag) && 765 (1 == ps_seq->s_vui.u1_bitstream_restriction_flag)) 766 { 767 if(ps_seq->u1_frame_mbs_only_flag == 1) 768 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames + 1; 769 else 770 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames * 2 + 2; 771 } 772 773 if(IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode) 774 ps_dec->i4_display_delay = 0; 775 776 if(ps_dec->u4_share_disp_buf == 0) 777 { 778 if(ps_seq->u1_frame_mbs_only_flag == 1) 779 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames + 1; 780 else 781 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames * 2 + 2; 782 } 783 else 784 { 785 ps_dec->u1_pic_bufs = (WORD32)ps_dec->u4_num_disp_bufs; 786 } 787 788 /* Ensure at least two buffers are allocated */ 789 ps_dec->u1_pic_bufs = MAX(ps_dec->u1_pic_bufs, 2); 790 791 if(ps_dec->u4_share_disp_buf == 0) 792 ps_dec->u1_pic_bufs = MIN(ps_dec->u1_pic_bufs, 793 (H264_MAX_REF_PICS * 2)); 794 795 ps_dec->u1_max_dec_frame_buffering = MIN( 796 ps_dec->u1_max_dec_frame_buffering, 797 ps_dec->u1_pic_bufs); 798 799 /* Temporary hack to run Tractor Cav/Cab/MbAff Profiler streams also for CAFI1_SVA_C.264 in conformance*/ 800 if(ps_dec->u1_init_dec_flag) 801 { 802 ih264d_release_pics_in_dpb((void *)ps_dec, 803 ps_dec->u1_pic_bufs); 804 ih264d_release_display_bufs(ps_dec); 805 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr); 806 } 807 808 /*********************************************************************/ 809 /* Configuring decoder parameters based on level and then */ 810 /* fresh pointer initialisation in decoder scratch and state buffers */ 811 /*********************************************************************/ 812 if(!ps_dec->u1_init_dec_flag || 813 ((ps_seq->u1_level_idc < H264_LEVEL_3_0) ^ (ps_prev_seq_params->u1_level_idc < H264_LEVEL_3_0))) 814 { 815 ret = ih264d_init_dec_mb_grp(ps_dec); 816 if(ret != OK) 817 return ret; 818 } 819 820 ret = ih264d_allocate_dynamic_bufs(ps_dec); 821 if(ret != OK) 822 { 823 /* Free any dynamic buffers that are allocated */ 824 ih264d_free_dynamic_bufs(ps_dec); 825 ps_dec->i4_error_code = IVD_MEM_ALLOC_FAILED; 826 return IVD_MEM_ALLOC_FAILED; 827 } 828 829 ret = ih264d_create_pic_buffers(ps_dec->u1_pic_bufs, 830 ps_dec); 831 if(ret != OK) 832 return ret; 833 834 835 836 ret = ih264d_create_mv_bank(ps_dec, ps_dec->u2_pic_wd, 837 ps_dec->u2_pic_ht); 838 if(ret != OK) 839 return ret; 840 841 /* In shared mode, set all of them as used by display */ 842 if(ps_dec->u4_share_disp_buf == 1) 843 { 844 WORD32 i; 845 846 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 847 { 848 ih264_buf_mgr_set_status((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i, 849 BUF_MGR_IO); 850 } 851 } 852 853 ps_dec->u1_init_dec_flag = 1; 854 ps_prev_seq_params->u2_frm_wd_in_mbs = ps_seq->u2_frm_wd_in_mbs; 855 ps_prev_seq_params->u1_level_idc = ps_seq->u1_level_idc; 856 ps_prev_seq_params->u1_profile_idc = ps_seq->u1_profile_idc; 857 ps_prev_seq_params->u2_frm_ht_in_mbs = ps_seq->u2_frm_ht_in_mbs; 858 ps_prev_seq_params->u1_frame_mbs_only_flag = 859 ps_seq->u1_frame_mbs_only_flag; 860 ps_prev_seq_params->u1_direct_8x8_inference_flag = 861 ps_seq->u1_direct_8x8_inference_flag; 862 863 ps_dec->i4_cur_display_seq = 0; 864 ps_dec->i4_prev_max_display_seq = 0; 865 ps_dec->i4_max_poc = 0; 866 867 { 868 /* 0th entry of CtxtIncMbMap will be always be containing default values 869 for CABAC context representing MB not available */ 870 ctxt_inc_mb_info_t *p_DefCtxt = ps_dec->p_ctxt_inc_mb_map - 1; 871 UWORD8 *pu1_temp; 872 WORD8 i; 873 p_DefCtxt->u1_mb_type = CAB_SKIP; 874 875 p_DefCtxt->u1_cbp = 0x0f; 876 p_DefCtxt->u1_intra_chroma_pred_mode = 0; 877 878 p_DefCtxt->u1_yuv_dc_csbp = 0x7; 879 880 p_DefCtxt->u1_transform8x8_ctxt = 0; 881 882 pu1_temp = (UWORD8*)p_DefCtxt->i1_ref_idx; 883 for(i = 0; i < 4; i++, pu1_temp++) 884 (*pu1_temp) = 0; 885 pu1_temp = (UWORD8*)p_DefCtxt->u1_mv; 886 for(i = 0; i < 16; i++, pu1_temp++) 887 (*pu1_temp) = 0; 888 ps_dec->ps_def_ctxt_mb_info = p_DefCtxt; 889 } 890 891 } 892 /* reset DBP commands read u4_flag */ 893 ps_dec->ps_dpb_cmds->u1_dpb_commands_read = 0; 894 895 return OK; 896 } 897 898 /*****************************************************************************/ 899 /* */ 900 /* Function Name : ih264d_get_next_display_field */ 901 /* */ 902 /* Description : Application calls this module to get the next field */ 903 /* to be displayed */ 904 /* */ 905 /* Inputs : 1. IBUFAPI_Handle Hnadle to the Display buffer */ 906 /* 2. IH264DEC_DispUnit Pointer to the display struct */ 907 /* */ 908 /* Globals : */ 909 /* */ 910 /* */ 911 /* Processing : None */ 912 /* Outputs : None */ 913 /* Returns : None */ 914 /* Issues : None */ 915 /* */ 916 /* Revision History: */ 917 /* */ 918 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 919 /* 27 05 2005 Ittiam Draft */ 920 /* */ 921 /*****************************************************************************/ 922 923 WORD32 ih264d_get_next_display_field(dec_struct_t * ps_dec, 924 ivd_out_bufdesc_t *ps_out_buffer, 925 ivd_get_display_frame_op_t *pv_disp_op) 926 { 927 pic_buffer_t *pic_buf; 928 929 UWORD8 i1_cur_fld; 930 WORD32 u4_api_ret = -1; 931 WORD32 i4_disp_buf_id; 932 iv_yuv_buf_t *ps_op_frm; 933 934 935 936 ps_op_frm = &(ps_dec->s_disp_frame_info); 937 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 938 pic_buf = (pic_buffer_t *)ih264_disp_mgr_get( 939 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, &i4_disp_buf_id); 940 ps_dec->u4_num_fld_in_frm = 0; 941 u4_api_ret = -1; 942 pv_disp_op->u4_ts = 0; 943 pv_disp_op->e_output_format = ps_dec->u1_chroma_format; 944 945 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_out_buffer->pu1_bufs[0]; 946 pv_disp_op->s_disp_frm_buf.pv_u_buf = ps_out_buffer->pu1_bufs[1]; 947 pv_disp_op->s_disp_frm_buf.pv_v_buf = ps_out_buffer->pu1_bufs[2]; 948 if(pic_buf != NULL) 949 { 950 pv_disp_op->e4_fld_type = 0; 951 pv_disp_op->u4_disp_buf_id = i4_disp_buf_id; 952 953 ps_op_frm->u4_y_ht = pic_buf->u2_disp_height << 1; 954 ps_op_frm->u4_u_ht = ps_op_frm->u4_v_ht = ps_op_frm->u4_y_ht >> 1; 955 ps_op_frm->u4_y_wd = pic_buf->u2_disp_width; 956 957 ps_op_frm->u4_u_wd = ps_op_frm->u4_v_wd = ps_op_frm->u4_y_wd >> 1; 958 959 ps_op_frm->u4_y_strd = pic_buf->u2_frm_wd_y; 960 ps_op_frm->u4_u_strd = ps_op_frm->u4_v_strd = pic_buf->u2_frm_wd_uv; 961 962 /* ! */ 963 pv_disp_op->u4_ts = pic_buf->u4_ts; 964 965 /* set the start of the Y, U and V buffer pointer for display */ 966 ps_op_frm->pv_y_buf = pic_buf->pu1_buf1 + pic_buf->u2_crop_offset_y; 967 ps_op_frm->pv_u_buf = pic_buf->pu1_buf2 + pic_buf->u2_crop_offset_uv; 968 ps_op_frm->pv_v_buf = pic_buf->pu1_buf3 + pic_buf->u2_crop_offset_uv; 969 ps_dec->u4_num_fld_in_frm++; 970 ps_dec->u4_num_fld_in_frm++; 971 u4_api_ret = 0; 972 973 if(pic_buf->u1_picturetype == 0) 974 pv_disp_op->u4_progressive_frame_flag = 1; 975 else 976 pv_disp_op->u4_progressive_frame_flag = 0; 977 978 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 979 pv_disp_op->u4_error_code = u4_api_ret; 980 pv_disp_op->e_pic_type = 0xFFFFFFFF; //Junk; 981 982 if(u4_api_ret) 983 { 984 pv_disp_op->u4_error_code = 1; //put a proper error code here 985 } 986 else 987 { 988 989 //Release the buffer if being sent for display 990 UWORD32 temp; 991 UWORD32 dest_inc_Y = 0, dest_inc_UV = 0; 992 993 pv_disp_op->s_disp_frm_buf.u4_y_wd = temp = MIN(ps_op_frm->u4_y_wd, 994 ps_op_frm->u4_y_strd); 995 pv_disp_op->s_disp_frm_buf.u4_u_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd 996 >> 1; 997 pv_disp_op->s_disp_frm_buf.u4_v_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd 998 >> 1; 999 1000 pv_disp_op->s_disp_frm_buf.u4_y_ht = ps_op_frm->u4_y_ht; 1001 pv_disp_op->s_disp_frm_buf.u4_u_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht 1002 >> 1; 1003 pv_disp_op->s_disp_frm_buf.u4_v_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht 1004 >> 1; 1005 if(0 == ps_dec->u4_share_disp_buf) 1006 { 1007 pv_disp_op->s_disp_frm_buf.u4_y_strd = 1008 pv_disp_op->s_disp_frm_buf.u4_y_wd; 1009 pv_disp_op->s_disp_frm_buf.u4_u_strd = 1010 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1; 1011 pv_disp_op->s_disp_frm_buf.u4_v_strd = 1012 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1; 1013 1014 } 1015 else 1016 { 1017 pv_disp_op->s_disp_frm_buf.u4_y_strd = ps_op_frm->u4_y_strd; 1018 } 1019 1020 if(ps_dec->u4_app_disp_width) 1021 { 1022 pv_disp_op->s_disp_frm_buf.u4_y_strd = MAX( 1023 ps_dec->u4_app_disp_width, 1024 pv_disp_op->s_disp_frm_buf.u4_y_strd); 1025 } 1026 1027 pv_disp_op->u4_error_code = 0; 1028 if(pv_disp_op->e_output_format == IV_YUV_420P) 1029 { 1030 UWORD32 i; 1031 pv_disp_op->s_disp_frm_buf.u4_u_strd = 1032 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1; 1033 pv_disp_op->s_disp_frm_buf.u4_v_strd = 1034 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1; 1035 1036 pv_disp_op->s_disp_frm_buf.u4_u_wd = ps_op_frm->u4_y_wd >> 1; 1037 pv_disp_op->s_disp_frm_buf.u4_v_wd = ps_op_frm->u4_y_wd >> 1; 1038 1039 if(1 == ps_dec->u4_share_disp_buf) 1040 { 1041 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf; 1042 1043 for(i = 0; i < MAX_DISP_BUFS_NEW; i++) 1044 { 1045 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0]; 1046 buf += ps_dec->disp_bufs[i].u4_ofst[0]; 1047 if(((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf 1048 - pic_buf->u2_crop_offset_y) == buf) 1049 { 1050 buf = ps_dec->disp_bufs[i].buf[1]; 1051 buf += ps_dec->disp_bufs[i].u4_ofst[1]; 1052 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf 1053 + (pic_buf->u2_crop_offset_uv 1054 / YUV420SP_FACTOR); 1055 1056 buf = ps_dec->disp_bufs[i].buf[2]; 1057 buf += ps_dec->disp_bufs[i].u4_ofst[2]; 1058 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf 1059 + (pic_buf->u2_crop_offset_uv 1060 / YUV420SP_FACTOR); 1061 1062 } 1063 } 1064 } 1065 1066 } 1067 else if((pv_disp_op->e_output_format == IV_YUV_420SP_UV) 1068 || (pv_disp_op->e_output_format == IV_YUV_420SP_VU)) 1069 { 1070 pv_disp_op->s_disp_frm_buf.u4_u_strd = 1071 pv_disp_op->s_disp_frm_buf.u4_y_strd; 1072 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0; 1073 1074 if(1 == ps_dec->u4_share_disp_buf) 1075 { 1076 UWORD32 i; 1077 1078 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf; 1079 1080 for(i = 0; i < MAX_DISP_BUFS_NEW; i++) 1081 { 1082 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0]; 1083 buf += ps_dec->disp_bufs[i].u4_ofst[0]; 1084 if((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf 1085 - pic_buf->u2_crop_offset_y == buf) 1086 { 1087 buf = ps_dec->disp_bufs[i].buf[1]; 1088 buf += ps_dec->disp_bufs[i].u4_ofst[1]; 1089 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf 1090 + pic_buf->u2_crop_offset_uv; 1091 ; 1092 1093 buf = ps_dec->disp_bufs[i].buf[2]; 1094 buf += ps_dec->disp_bufs[i].u4_ofst[2]; 1095 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf 1096 + pic_buf->u2_crop_offset_uv; 1097 ; 1098 } 1099 } 1100 } 1101 pv_disp_op->s_disp_frm_buf.u4_u_wd = 1102 pv_disp_op->s_disp_frm_buf.u4_y_wd; 1103 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0; 1104 1105 } 1106 else if((pv_disp_op->e_output_format == IV_RGB_565) 1107 || (pv_disp_op->e_output_format == IV_YUV_422ILE)) 1108 { 1109 1110 pv_disp_op->s_disp_frm_buf.u4_u_strd = 0; 1111 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0; 1112 pv_disp_op->s_disp_frm_buf.u4_u_wd = 0; 1113 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0; 1114 pv_disp_op->s_disp_frm_buf.u4_u_ht = 0; 1115 pv_disp_op->s_disp_frm_buf.u4_v_ht = 0; 1116 1117 } 1118 1119 1120 } 1121 1122 return u4_api_ret; 1123 } 1124 1125 1126 /*****************************************************************************/ 1127 /* Function Name : ih264d_release_display_field */ 1128 /* */ 1129 /* Description : This function releases the display field that was returned */ 1130 /* here. */ 1131 /* Inputs : ps_dec - Decoder parameters */ 1132 /* Globals : None */ 1133 /* Processing : Refer bumping process in the standard */ 1134 /* Outputs : Assigns display sequence number. */ 1135 /* Returns : None */ 1136 /* */ 1137 /* Issues : None */ 1138 /* */ 1139 /* Revision History: */ 1140 /* */ 1141 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1142 /* 27 04 2005 NS Draft */ 1143 /* */ 1144 /*****************************************************************************/ 1145 void ih264d_release_display_field(dec_struct_t *ps_dec, 1146 ivd_get_display_frame_op_t *pv_disp_op) 1147 { 1148 if(1 == pv_disp_op->u4_error_code) 1149 { 1150 if(1 == ps_dec->u1_flushfrm) 1151 { 1152 UWORD32 i; 1153 1154 if(1 == ps_dec->u4_share_disp_buf) 1155 { 1156 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 1157 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++) 1158 { 1159 if(1 == ps_dec->u4_disp_buf_mapping[i]) 1160 { 1161 ih264_buf_mgr_release( 1162 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i, 1163 BUF_MGR_IO); 1164 ps_dec->u4_disp_buf_mapping[i] = 0; 1165 } 1166 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 1167 1168 memset(ps_dec->u4_disp_buf_to_be_freed, 0, 1169 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1170 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 1171 ps_dec->u4_disp_buf_mapping[i] = 1; 1172 } 1173 ps_dec->u1_flushfrm = 0; 1174 1175 } 1176 } 1177 else 1178 { 1179 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 1180 1181 if(0 == ps_dec->u4_share_disp_buf) 1182 { 1183 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1184 pv_disp_op->u4_disp_buf_id, 1185 BUF_MGR_IO); 1186 1187 } 1188 else 1189 { 1190 ps_dec->u4_disp_buf_mapping[pv_disp_op->u4_disp_buf_id] = 1; 1191 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 1192 1193 } 1194 } 1195 /*****************************************************************************/ 1196 /* Function Name : ih264d_assign_display_seq */ 1197 /* */ 1198 /* Description : This function implments bumping process. Every outgoing */ 1199 /* frame from DPB is assigned a display sequence number */ 1200 /* which increases monotonically. System looks for this */ 1201 /* number to display a frame. */ 1202 /* here. */ 1203 /* Inputs : ps_dec - Decoder parameters */ 1204 /* Globals : None */ 1205 /* Processing : Refer bumping process in the standard */ 1206 /* Outputs : Assigns display sequence number. */ 1207 /* Returns : None */ 1208 /* */ 1209 /* Issues : None */ 1210 /* */ 1211 /* Revision History: */ 1212 /* */ 1213 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1214 /* 27 04 2005 NS Draft */ 1215 /* */ 1216 /*****************************************************************************/ 1217 WORD32 ih264d_assign_display_seq(dec_struct_t *ps_dec) 1218 { 1219 WORD32 i; 1220 WORD32 i4_min_poc; 1221 WORD32 i4_min_poc_buf_id; 1222 WORD32 i4_min_index; 1223 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1224 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map; 1225 1226 i4_min_poc = 0x7fffffff; 1227 i4_min_poc_buf_id = -1; 1228 i4_min_index = -1; 1229 1230 if(ps_dpb_mgr->i1_poc_buf_id_entries >= ps_dec->i4_display_delay) 1231 { 1232 for(i = 0; i < MAX_FRAMES; i++) 1233 { 1234 if((i4_poc_buf_id_map[i][0] != -1) 1235 && (DO_NOT_DISP 1236 != ps_dpb_mgr->ai4_poc_buf_id_map[i][0])) 1237 { 1238 if(i4_poc_buf_id_map[i][1] < i4_min_poc) 1239 { 1240 i4_min_poc = i4_poc_buf_id_map[i][1]; 1241 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0]; 1242 i4_min_index = i; 1243 } 1244 } 1245 } 1246 1247 if((i4_min_index != -1) && (DO_NOT_DISP != i4_min_poc_buf_id)) 1248 { 1249 ps_dec->i4_cur_display_seq++; 1250 ih264_disp_mgr_add( 1251 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, 1252 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq, 1253 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]); 1254 i4_poc_buf_id_map[i4_min_index][0] = -1; 1255 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1256 ps_dpb_mgr->i1_poc_buf_id_entries--; 1257 } 1258 else if(DO_NOT_DISP == i4_min_poc_buf_id) 1259 { 1260 WORD32 i4_error_code; 1261 i4_error_code = ERROR_GAPS_IN_FRM_NUM; 1262 // i4_error_code |= 1<<IVD_CORRUPTEDDATA; 1263 return i4_error_code; 1264 } 1265 } 1266 return OK; 1267 } 1268 1269 /*****************************************************************************/ 1270 /* */ 1271 /* Function Name : ih264d_release_display_bufs */ 1272 /* */ 1273 /* Description : This function implments bumping process when mmco = 5. */ 1274 /* Each outgoing frame from DPB is assigned a display */ 1275 /* sequence number which increases monotonically. System */ 1276 /* looks for this number to display a frame. */ 1277 /* Inputs : ps_dec - Decoder parameters */ 1278 /* Globals : None */ 1279 /* Processing : Refer bumping process in the standard for mmco = 5 */ 1280 /* Outputs : Assigns display sequence number. */ 1281 /* Returns : None */ 1282 /* */ 1283 /* Issues : None */ 1284 /* */ 1285 /* Revision History: */ 1286 /* */ 1287 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1288 /* 27 04 2005 NS Draft */ 1289 /* */ 1290 /*****************************************************************************/ 1291 void ih264d_release_display_bufs(dec_struct_t *ps_dec) 1292 { 1293 WORD32 i, j; 1294 WORD32 i4_min_poc; 1295 WORD32 i4_min_poc_buf_id; 1296 WORD32 i4_min_index; 1297 UWORD64 u8_temp; 1298 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1299 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map; 1300 1301 i4_min_poc = 0x7fffffff; 1302 i4_min_poc_buf_id = -1; 1303 i4_min_index = -1; 1304 1305 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1306 1307 for(j = 0; j < ps_dpb_mgr->i1_poc_buf_id_entries; j++) 1308 { 1309 i4_min_poc = 0x7fffffff; 1310 for(i = 0; i < MAX_FRAMES; i++) 1311 { 1312 if(i4_poc_buf_id_map[i][0] != -1) 1313 { 1314 if(i4_poc_buf_id_map[i][1] < i4_min_poc) 1315 { 1316 i4_min_poc = i4_poc_buf_id_map[i][1]; 1317 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0]; 1318 i4_min_index = i; 1319 } 1320 } 1321 } 1322 1323 if(DO_NOT_DISP != i4_min_poc_buf_id) 1324 { 1325 ps_dec->i4_cur_display_seq++; 1326 ih264_disp_mgr_add( 1327 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, 1328 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq, 1329 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]); 1330 i4_poc_buf_id_map[i4_min_index][0] = -1; 1331 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1332 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0; 1333 } 1334 else 1335 { 1336 i4_poc_buf_id_map[i4_min_index][0] = -1; 1337 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1338 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0; 1339 } 1340 } 1341 ps_dpb_mgr->i1_poc_buf_id_entries = 0; 1342 u8_temp = (UWORD64)ps_dec->i4_prev_max_display_seq + ps_dec->i4_max_poc 1343 + ps_dec->u1_max_dec_frame_buffering + 1; 1344 /*If i4_prev_max_display_seq overflows integer range, reset it */ 1345 ps_dec->i4_prev_max_display_seq = (u8_temp > 0x7fffffff)? 1346 0 : u8_temp; 1347 ps_dec->i4_max_poc = 0; 1348 } 1349 1350 /*****************************************************************************/ 1351 /* */ 1352 /* Function Name : ih264d_assign_pic_num */ 1353 /* */ 1354 /* Description : This function assigns pic num to each reference frame */ 1355 /* depending on the cur_frame_num as speified in section */ 1356 /* 8.2.4.1 */ 1357 /* */ 1358 /* Inputs : ps_dec */ 1359 /* */ 1360 /* Globals : NO globals used */ 1361 /* */ 1362 /* Processing : for all ST pictures */ 1363 /* if( FrameNum > cur_frame_num) */ 1364 /* PicNum = FrameNum - MaxFrameNum */ 1365 /* else */ 1366 /* PicNum = FrameNum */ 1367 /* */ 1368 /* Returns : void */ 1369 /* */ 1370 /* Issues : NO */ 1371 /* */ 1372 /* Revision History: */ 1373 /* */ 1374 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1375 /* 13 07 2002 Jay Draft */ 1376 /* */ 1377 /*****************************************************************************/ 1378 1379 void ih264d_assign_pic_num(dec_struct_t *ps_dec) 1380 { 1381 dpb_manager_t *ps_dpb_mgr; 1382 struct dpb_info_t *ps_next_dpb; 1383 WORD8 i; 1384 WORD32 i4_cur_frame_num, i4_max_frame_num; 1385 WORD32 i4_ref_frame_num; 1386 UWORD8 u1_fld_pic_flag = ps_dec->ps_cur_slice->u1_field_pic_flag; 1387 1388 i4_max_frame_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1; 1389 i4_cur_frame_num = ps_dec->ps_cur_pic->i4_frame_num; 1390 ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1391 1392 /* Start from ST head */ 1393 ps_next_dpb = ps_dpb_mgr->ps_dpb_st_head; 1394 for(i = 0; i < ps_dpb_mgr->u1_num_st_ref_bufs; i++) 1395 { 1396 WORD32 i4_pic_num; 1397 1398 i4_ref_frame_num = ps_next_dpb->ps_pic_buf->i4_frame_num; 1399 if(i4_ref_frame_num > i4_cur_frame_num) 1400 { 1401 /* RefPic Buf frame_num is before Current frame_num in decode order */ 1402 i4_pic_num = i4_ref_frame_num - i4_max_frame_num; 1403 } 1404 else 1405 { 1406 /* RefPic Buf frame_num is after Current frame_num in decode order */ 1407 i4_pic_num = i4_ref_frame_num; 1408 } 1409 1410 ps_next_dpb->ps_pic_buf->i4_pic_num = i4_pic_num; 1411 ps_next_dpb->i4_frame_num = i4_pic_num; 1412 ps_next_dpb->ps_pic_buf->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1413 if(u1_fld_pic_flag) 1414 { 1415 /* Assign the pic num to top fields and bot fields */ 1416 1417 ps_next_dpb->s_top_field.i4_pic_num = i4_pic_num * 2 1418 + !(ps_dec->ps_cur_slice->u1_bottom_field_flag); 1419 ps_next_dpb->s_bot_field.i4_pic_num = i4_pic_num * 2 1420 + ps_dec->ps_cur_slice->u1_bottom_field_flag; 1421 } 1422 /* Chase the next link */ 1423 ps_next_dpb = ps_next_dpb->ps_prev_short; 1424 } 1425 1426 if(ps_dec->ps_cur_sps->u1_gaps_in_frame_num_value_allowed_flag 1427 && ps_dpb_mgr->u1_num_gaps) 1428 { 1429 WORD32 i4_start_frm, i4_end_frm; 1430 /* Assign pic numbers for gaps */ 1431 for(i = 0; i < MAX_FRAMES; i++) 1432 { 1433 i4_start_frm = ps_dpb_mgr->ai4_gaps_start_frm_num[i]; 1434 if(i4_start_frm != INVALID_FRAME_NUM) 1435 { 1436 if(i4_start_frm > i4_cur_frame_num) 1437 { 1438 /* gap's frame_num is before Current frame_num in 1439 decode order */ 1440 i4_start_frm -= i4_max_frame_num; 1441 } 1442 ps_dpb_mgr->ai4_gaps_start_frm_num[i] = i4_start_frm; 1443 i4_end_frm = ps_dpb_mgr->ai4_gaps_end_frm_num[i]; 1444 1445 if(i4_end_frm > i4_cur_frame_num) 1446 { 1447 /* gap's frame_num is before Current frame_num in 1448 decode order */ 1449 i4_end_frm -= i4_max_frame_num; 1450 } 1451 ps_dpb_mgr->ai4_gaps_end_frm_num[i] = i4_end_frm; 1452 } 1453 } 1454 } 1455 } 1456 1457 /*! 1458 ************************************************************************** 1459 * \if Function name : ih264d_update_qp \endif 1460 * 1461 * \brief 1462 * Updates the values of QP and its related entities 1463 * 1464 * \return 1465 * 0 on Success and Error code otherwise 1466 * 1467 ************************************************************************** 1468 */ 1469 WORD32 ih264d_update_qp(dec_struct_t * ps_dec, const WORD8 i1_qp) 1470 { 1471 WORD32 i_temp; 1472 i_temp = (ps_dec->u1_qp + i1_qp + 52) % 52; 1473 1474 if((i_temp < 0) || (i_temp > 51) || (i1_qp < -26) || (i1_qp > 25)) 1475 return ERROR_INV_RANGE_QP_T; 1476 1477 ps_dec->u1_qp = i_temp; 1478 ps_dec->u1_qp_y_rem6 = ps_dec->u1_qp % 6; 1479 ps_dec->u1_qp_y_div6 = ps_dec->u1_qp / 6; 1480 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_chroma_qp_index_offset); 1481 ps_dec->u1_qp_u_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1482 ps_dec->u1_qp_u_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1483 1484 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_second_chroma_qp_index_offset); 1485 ps_dec->u1_qp_v_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1486 ps_dec->u1_qp_v_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1487 1488 ps_dec->pu2_quant_scale_y = 1489 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_y_rem6]; 1490 ps_dec->pu2_quant_scale_u = 1491 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_u_rem6]; 1492 ps_dec->pu2_quant_scale_v = 1493 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_v_rem6]; 1494 return OK; 1495 } 1496 1497 /*****************************************************************************/ 1498 /* */ 1499 /* Function Name : ih264d_decode_gaps_in_frame_num */ 1500 /* */ 1501 /* Description : This function decodes gaps in frame number */ 1502 /* */ 1503 /* Inputs : ps_dec Decoder parameters */ 1504 /* u2_frame_num current frame number */ 1505 /* */ 1506 /* Globals : None */ 1507 /* Processing : This functionality needs to be implemented */ 1508 /* Outputs : None */ 1509 /* Returns : None */ 1510 /* */ 1511 /* Issues : Not implemented */ 1512 /* */ 1513 /* Revision History: */ 1514 /* */ 1515 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1516 /* 06 05 2002 NS Draft */ 1517 /* */ 1518 /*****************************************************************************/ 1519 WORD32 ih264d_decode_gaps_in_frame_num(dec_struct_t *ps_dec, 1520 UWORD16 u2_frame_num) 1521 { 1522 UWORD32 u4_next_frm_num, u4_start_frm_num; 1523 UWORD32 u4_max_frm_num; 1524 pocstruct_t s_tmp_poc; 1525 WORD32 i4_poc; 1526 dec_slice_params_t *ps_cur_slice; 1527 1528 dec_pic_params_t *ps_pic_params; 1529 WORD8 i1_gap_idx; 1530 WORD32 *i4_gaps_start_frm_num; 1531 dpb_manager_t *ps_dpb_mgr; 1532 WORD32 i4_frame_gaps; 1533 WORD8 *pi1_gaps_per_seq; 1534 WORD32 ret; 1535 1536 ps_cur_slice = ps_dec->ps_cur_slice; 1537 if(ps_cur_slice->u1_field_pic_flag) 1538 { 1539 if(ps_dec->u2_prev_ref_frame_num == u2_frame_num) 1540 return 0; 1541 } 1542 1543 u4_next_frm_num = ps_dec->u2_prev_ref_frame_num + 1; 1544 u4_max_frm_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1; 1545 1546 // check 1547 if(u4_next_frm_num >= u4_max_frm_num) 1548 { 1549 u4_next_frm_num -= u4_max_frm_num; 1550 } 1551 1552 if(u4_next_frm_num == u2_frame_num) 1553 { 1554 return (0); 1555 } 1556 1557 // check 1558 if((ps_dec->u1_nal_unit_type == IDR_SLICE_NAL) 1559 && (u4_next_frm_num >= u2_frame_num)) 1560 { 1561 return (0); 1562 } 1563 u4_start_frm_num = u4_next_frm_num; 1564 1565 s_tmp_poc.i4_pic_order_cnt_lsb = 0; 1566 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0; 1567 s_tmp_poc.i4_pic_order_cnt_lsb = 0; 1568 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0; 1569 s_tmp_poc.i4_delta_pic_order_cnt[0] = 0; 1570 s_tmp_poc.i4_delta_pic_order_cnt[1] = 0; 1571 1572 ps_cur_slice = ps_dec->ps_cur_slice; 1573 ps_pic_params = ps_dec->ps_cur_pps; 1574 1575 i4_frame_gaps = 0; 1576 ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1577 1578 /* Find a empty slot to store gap seqn info */ 1579 i4_gaps_start_frm_num = ps_dpb_mgr->ai4_gaps_start_frm_num; 1580 for(i1_gap_idx = 0; i1_gap_idx < MAX_FRAMES; i1_gap_idx++) 1581 { 1582 if(INVALID_FRAME_NUM == i4_gaps_start_frm_num[i1_gap_idx]) 1583 break; 1584 } 1585 if(MAX_FRAMES == i1_gap_idx) 1586 { 1587 UWORD32 i4_error_code; 1588 i4_error_code = ERROR_DBP_MANAGER_T; 1589 // i4_error_code |= 1<<IVD_CORRUPTEDDATA; 1590 return i4_error_code; 1591 } 1592 1593 i4_poc = 0; 1594 i4_gaps_start_frm_num[i1_gap_idx] = u4_start_frm_num; 1595 ps_dpb_mgr->ai4_gaps_end_frm_num[i1_gap_idx] = u2_frame_num - 1; 1596 pi1_gaps_per_seq = ps_dpb_mgr->ai1_gaps_per_seq; 1597 pi1_gaps_per_seq[i1_gap_idx] = 0; 1598 while(u4_next_frm_num != u2_frame_num) 1599 { 1600 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1601 if(ps_pic_params->ps_sps->u1_pic_order_cnt_type) 1602 { 1603 /* allocate a picture buffer and insert it as ST node */ 1604 ret = ih264d_decode_pic_order_cnt(0, u4_next_frm_num, 1605 &ps_dec->s_prev_pic_poc, 1606 &s_tmp_poc, ps_cur_slice, 1607 ps_pic_params, 1, 0, 0, 1608 &i4_poc); 1609 if(ret != OK) 1610 return ret; 1611 1612 /* Display seq no calculations */ 1613 if(i4_poc >= ps_dec->i4_max_poc) 1614 ps_dec->i4_max_poc = i4_poc; 1615 /* IDR Picture or POC wrap around */ 1616 if(i4_poc == 0) 1617 { 1618 UWORD64 u8_temp; 1619 u8_temp = (UWORD64)ps_dec->i4_prev_max_display_seq 1620 + ps_dec->i4_max_poc 1621 + ps_dec->u1_max_dec_frame_buffering + 1; 1622 /*If i4_prev_max_display_seq overflows integer range, reset it */ 1623 ps_dec->i4_prev_max_display_seq = (u8_temp > 0x7fffffff)? 1624 0 : u8_temp; 1625 ps_dec->i4_max_poc = 0; 1626 } 1627 1628 ps_cur_slice->u1_mmco_equalto5 = 0; 1629 ps_cur_slice->u2_frame_num = u4_next_frm_num; 1630 } 1631 1632 // check 1633 if(ps_dpb_mgr->i1_poc_buf_id_entries 1634 >= ps_dec->u1_max_dec_frame_buffering) 1635 { 1636 ret = ih264d_assign_display_seq(ps_dec); 1637 if(ret != OK) 1638 return ret; 1639 } 1640 1641 ret = ih264d_insert_pic_in_display_list( 1642 ps_dec->ps_dpb_mgr, (WORD8) DO_NOT_DISP, 1643 (WORD32)(ps_dec->i4_prev_max_display_seq + i4_poc), 1644 u4_next_frm_num); 1645 if(ret != OK) 1646 return ret; 1647 1648 pi1_gaps_per_seq[i1_gap_idx]++; 1649 ret = ih264d_do_mmco_for_gaps(ps_dpb_mgr, 1650 ps_dec->ps_cur_sps->u1_num_ref_frames); 1651 if(ret != OK) 1652 return ret; 1653 1654 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1655 1656 u4_next_frm_num++; 1657 if(u4_next_frm_num >= u4_max_frm_num) 1658 { 1659 u4_next_frm_num -= u4_max_frm_num; 1660 } 1661 1662 i4_frame_gaps++; 1663 } 1664 1665 return OK; 1666 } 1667 1668 /*! 1669 ************************************************************************** 1670 * \if Function name : ih264d_create_pic_buffers \endif 1671 * 1672 * \brief 1673 * This function creates Picture Buffers. 1674 * 1675 * \return 1676 * 0 on Success and -1 on error 1677 ************************************************************************** 1678 */ 1679 WORD32 ih264d_create_pic_buffers(UWORD8 u1_num_of_buf, 1680 dec_struct_t *ps_dec) 1681 { 1682 struct pic_buffer_t *ps_pic_buf; 1683 UWORD8 i; 1684 UWORD32 u4_luma_size, u4_chroma_size; 1685 UWORD8 u1_frm = ps_dec->ps_cur_sps->u1_frame_mbs_only_flag; 1686 WORD32 j; 1687 UWORD8 *pu1_buf; 1688 1689 ps_pic_buf = ps_dec->ps_pic_buf_base; 1690 ih264_disp_mgr_init((disp_mgr_t *)ps_dec->pv_disp_buf_mgr); 1691 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_pic_buf_mgr); 1692 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y; 1693 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv; 1694 1695 { 1696 if(ps_dec->u4_share_disp_buf == 1) 1697 { 1698 /* In case of buffers getting shared between application and library 1699 there is no need of reference memtabs. Instead of setting the i4_size 1700 to zero, it is reduced to a small i4_size to ensure that changes 1701 in the code are minimal */ 1702 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 1703 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU) 1704 || (ps_dec->u1_chroma_format == IV_YUV_420P)) 1705 { 1706 u4_luma_size = 64; 1707 } 1708 1709 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 1710 { 1711 u4_chroma_size = 64; 1712 } 1713 1714 } 1715 } 1716 1717 pu1_buf = ps_dec->pu1_pic_buf_base; 1718 1719 /* Allocate memory for refernce buffers */ 1720 for(i = 0; i < u1_num_of_buf; i++) 1721 { 1722 UWORD32 u4_offset; 1723 WORD32 buf_ret; 1724 UWORD8 *pu1_luma, *pu1_chroma; 1725 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1726 1727 pu1_luma = pu1_buf; 1728 pu1_buf += ALIGN64(u4_luma_size); 1729 pu1_chroma = pu1_buf; 1730 pu1_buf += ALIGN64(u4_chroma_size); 1731 1732 /* Offset to the start of the pic from the top left corner of the frame 1733 buffer */ 1734 1735 if((0 == ps_dec->u4_share_disp_buf) 1736 || (NULL == ps_dec->disp_bufs[i].buf[0])) 1737 { 1738 UWORD32 pad_len_h, pad_len_v; 1739 1740 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H; 1741 ps_pic_buf->pu1_buf1 = (UWORD8 *)(pu1_luma) + u4_offset; 1742 1743 pad_len_h = MAX(PAD_LEN_UV_H, (PAD_LEN_Y_H >> 1)); 1744 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 1745 1746 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 1747 1748 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset; 1749 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset; 1750 1751 } 1752 else 1753 { 1754 UWORD32 pad_len_h, pad_len_v; 1755 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H; 1756 ps_pic_buf->pu1_buf1 = (UWORD8 *)ps_dec->disp_bufs[i].buf[0] 1757 + u4_offset; 1758 1759 ps_dec->disp_bufs[i].u4_ofst[0] = u4_offset; 1760 1761 if(ps_dec->u1_chroma_format == IV_YUV_420P) 1762 { 1763 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR, 1764 (PAD_LEN_Y_H >> 1)); 1765 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 1766 1767 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 1768 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset; 1769 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset; 1770 1771 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset; 1772 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset; 1773 1774 } 1775 else 1776 { 1777 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR, 1778 (PAD_LEN_Y_H >> 1)); 1779 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 1780 1781 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 1782 ps_pic_buf->pu1_buf2 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1]) 1783 + u4_offset; 1784 ps_pic_buf->pu1_buf3 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1]) 1785 + u4_offset; 1786 1787 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset; 1788 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset; 1789 } 1790 } 1791 1792 ps_pic_buf->u2_frm_ht_y = ps_dec->u2_frm_ht_y; 1793 ps_pic_buf->u2_frm_ht_uv = ps_dec->u2_frm_ht_uv; 1794 ps_pic_buf->u2_frm_wd_y = ps_dec->u2_frm_wd_y; 1795 ps_pic_buf->u2_frm_wd_uv = ps_dec->u2_frm_wd_uv; 1796 1797 ps_pic_buf->u1_pic_buf_id = i; 1798 1799 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1800 ps_pic_buf, i); 1801 if(0 != buf_ret) 1802 { 1803 ps_dec->i4_error_code = ERROR_BUF_MGR; 1804 return ERROR_BUF_MGR; 1805 } 1806 1807 ps_dec->apv_buf_id_pic_buf_map[i] = (void *)ps_pic_buf; 1808 ps_pic_buf++; 1809 } 1810 1811 if(1 == ps_dec->u4_share_disp_buf) 1812 { 1813 for(i = 0; i < u1_num_of_buf; i++) 1814 ps_dec->u4_disp_buf_mapping[i] = 1; 1815 } 1816 return OK; 1817 } 1818 1819 /*! 1820 ************************************************************************** 1821 * \if Function name : ih264d_allocate_dynamic_bufs \endif 1822 * 1823 * \brief 1824 * This function allocates memory required by Decoder. 1825 * 1826 * \param ps_dec: Pointer to dec_struct_t. 1827 * 1828 * \return 1829 * Returns i4_status as returned by MemManager. 1830 * 1831 ************************************************************************** 1832 */ 1833 WORD16 ih264d_allocate_dynamic_bufs(dec_struct_t * ps_dec) 1834 { 1835 struct MemReq s_MemReq; 1836 struct MemBlock *p_MemBlock; 1837 1838 pred_info_t *ps_pred_frame; 1839 dec_mb_info_t *ps_frm_mb_info; 1840 dec_slice_struct_t *ps_dec_slice_buf; 1841 UWORD8 *pu1_dec_mb_map, *pu1_recon_mb_map; 1842 UWORD16 *pu2_slice_num_map; 1843 1844 WORD16 *pi16_res_coeff; 1845 WORD16 i16_status = 0; 1846 UWORD8 uc_frmOrFld = (1 - ps_dec->ps_cur_sps->u1_frame_mbs_only_flag); 1847 UWORD16 u4_luma_wd = ps_dec->u2_frm_wd_y; 1848 UWORD16 u4_chroma_wd = ps_dec->u2_frm_wd_uv; 1849 WORD8 c_i = 0; 1850 dec_seq_params_t *ps_sps = ps_dec->ps_cur_sps; 1851 UWORD32 u4_total_mbs = ps_sps->u2_total_num_of_mbs << uc_frmOrFld; 1852 UWORD32 u4_wd_mbs = ps_dec->u2_frm_wd_in_mbs; 1853 UWORD32 u4_ht_mbs = ps_dec->u2_frm_ht_in_mbs; 1854 UWORD32 u4_blk_wd; 1855 UWORD32 ui_size = 0; 1856 UWORD32 u4_int_scratch_size = 0, u4_ref_pred_size = 0; 1857 UWORD8 *pu1_buf; 1858 WORD32 num_entries; 1859 WORD32 size; 1860 void *pv_buf; 1861 UWORD32 u4_num_bufs; 1862 UWORD32 u4_luma_size, u4_chroma_size; 1863 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1864 1865 size = u4_total_mbs; 1866 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1867 RETURN_IF((NULL == pv_buf), IV_FAIL); 1868 memset(pv_buf, 0, size); 1869 ps_dec->pu1_dec_mb_map = pv_buf; 1870 1871 size = u4_total_mbs; 1872 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1873 RETURN_IF((NULL == pv_buf), IV_FAIL); 1874 memset(pv_buf, 0, size); 1875 ps_dec->pu1_recon_mb_map = pv_buf; 1876 1877 size = u4_total_mbs * sizeof(UWORD16); 1878 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1879 RETURN_IF((NULL == pv_buf), IV_FAIL); 1880 memset(pv_buf, 0, size); 1881 ps_dec->pu2_slice_num_map = pv_buf; 1882 1883 /************************************************************/ 1884 /* Post allocation Initialisations */ 1885 /************************************************************/ 1886 ps_dec->ps_parse_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 1887 ps_dec->ps_decode_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 1888 ps_dec->ps_computebs_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 1889 1890 ps_dec->ps_pred_start = ps_dec->ps_pred; 1891 1892 size = sizeof(parse_pmbarams_t) * (ps_dec->u1_recon_mb_grp); 1893 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1894 RETURN_IF((NULL == pv_buf), IV_FAIL); 1895 memset(pv_buf, 0, size); 1896 ps_dec->ps_parse_mb_data = pv_buf; 1897 1898 size = sizeof(parse_part_params_t) 1899 * ((ps_dec->u1_recon_mb_grp) << 4); 1900 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1901 RETURN_IF((NULL == pv_buf), IV_FAIL); 1902 memset(pv_buf, 0, size); 1903 ps_dec->ps_parse_part_params = pv_buf; 1904 1905 size = ((u4_wd_mbs * sizeof(deblkmb_neighbour_t)) << uc_frmOrFld); 1906 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1907 RETURN_IF((NULL == pv_buf), IV_FAIL); 1908 memset(pv_buf, 0, size); 1909 ps_dec->ps_deblk_top_mb = pv_buf; 1910 1911 size = ((sizeof(ctxt_inc_mb_info_t)) 1912 * (((u4_wd_mbs + 1) << uc_frmOrFld) + 1)); 1913 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1914 RETURN_IF((NULL == pv_buf), IV_FAIL); 1915 memset(pv_buf, 0, size); 1916 ps_dec->p_ctxt_inc_mb_map = pv_buf; 1917 1918 /* 0th entry of CtxtIncMbMap will be always be containing default values 1919 for CABAC context representing MB not available */ 1920 ps_dec->p_ctxt_inc_mb_map += 1; 1921 1922 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp 1923 * 16); 1924 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1925 RETURN_IF((NULL == pv_buf), IV_FAIL); 1926 memset(pv_buf, 0, size); 1927 ps_dec->ps_mv_p[0] = pv_buf; 1928 1929 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp 1930 * 16); 1931 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1932 RETURN_IF((NULL == pv_buf), IV_FAIL); 1933 memset(pv_buf, 0, size); 1934 ps_dec->ps_mv_p[1] = pv_buf; 1935 1936 { 1937 UWORD8 i; 1938 for(i = 0; i < MV_SCRATCH_BUFS; i++) 1939 { 1940 size = (sizeof(mv_pred_t) 1941 * ps_dec->u1_recon_mb_grp * 4); 1942 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1943 RETURN_IF((NULL == pv_buf), IV_FAIL); 1944 memset(pv_buf, 0, size); 1945 ps_dec->ps_mv_top_p[i] = pv_buf; 1946 } 1947 } 1948 1949 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2; 1950 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1951 RETURN_IF((NULL == pv_buf), IV_FAIL); 1952 ps_dec->pu1_y_intra_pred_line = pv_buf; 1953 memset(ps_dec->pu1_y_intra_pred_line, 0, size); 1954 ps_dec->pu1_y_intra_pred_line += MB_SIZE; 1955 1956 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2; 1957 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1958 RETURN_IF((NULL == pv_buf), IV_FAIL); 1959 ps_dec->pu1_u_intra_pred_line = pv_buf; 1960 memset(ps_dec->pu1_u_intra_pred_line, 0, size); 1961 ps_dec->pu1_u_intra_pred_line += MB_SIZE; 1962 1963 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2; 1964 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1965 RETURN_IF((NULL == pv_buf), IV_FAIL); 1966 ps_dec->pu1_v_intra_pred_line = pv_buf; 1967 memset(ps_dec->pu1_v_intra_pred_line, 0, size); 1968 ps_dec->pu1_v_intra_pred_line += MB_SIZE; 1969 1970 if(ps_dec->u1_separate_parse) 1971 { 1972 /* Needs one extra row of info, to hold top row data */ 1973 size = sizeof(mb_neigbour_params_t) 1974 * 2 * ((u4_wd_mbs + 2) * (u4_ht_mbs + 1)); 1975 } 1976 else 1977 { 1978 size = sizeof(mb_neigbour_params_t) 1979 * 2 * ((u4_wd_mbs + 2) << uc_frmOrFld); 1980 } 1981 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1982 RETURN_IF((NULL == pv_buf), IV_FAIL); 1983 1984 ps_dec->ps_nbr_mb_row = pv_buf; 1985 memset(ps_dec->ps_nbr_mb_row, 0, size); 1986 1987 /* Allocate deblock MB info */ 1988 size = (u4_total_mbs + u4_wd_mbs) * sizeof(deblk_mb_t); 1989 1990 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1991 RETURN_IF((NULL == pv_buf), IV_FAIL); 1992 ps_dec->ps_deblk_pic = pv_buf; 1993 1994 memset(ps_dec->ps_deblk_pic, 0, size); 1995 1996 /* Allocate frame level mb info */ 1997 size = sizeof(dec_mb_info_t) * u4_total_mbs; 1998 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1999 RETURN_IF((NULL == pv_buf), IV_FAIL); 2000 ps_dec->ps_frm_mb_info = pv_buf; 2001 memset(ps_dec->ps_frm_mb_info, 0, size); 2002 2003 /* Allocate memory for slice headers dec_slice_struct_t */ 2004 num_entries = MAX_FRAMES; 2005 if((1 >= ps_dec->ps_cur_sps->u1_num_ref_frames) && 2006 (0 == ps_dec->i4_display_delay)) 2007 { 2008 num_entries = 1; 2009 } 2010 num_entries = ((2 * num_entries) + 1); 2011 num_entries *= 2; 2012 2013 size = num_entries * sizeof(void *); 2014 size += PAD_MAP_IDX_POC * sizeof(void *); 2015 size *= u4_total_mbs; 2016 size += sizeof(dec_slice_struct_t) * u4_total_mbs; 2017 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2018 RETURN_IF((NULL == pv_buf), IV_FAIL); 2019 2020 ps_dec->ps_dec_slice_buf = pv_buf; 2021 memset(ps_dec->ps_dec_slice_buf, 0, size); 2022 pu1_buf = (UWORD8 *)ps_dec->ps_dec_slice_buf; 2023 pu1_buf += sizeof(dec_slice_struct_t) * u4_total_mbs; 2024 ps_dec->pv_map_ref_idx_to_poc_buf = (void *)pu1_buf; 2025 2026 /* Allocate memory for packed pred info */ 2027 num_entries = u4_total_mbs; 2028 num_entries *= 16 * 2; 2029 2030 size = sizeof(pred_info_pkd_t) * num_entries; 2031 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2032 RETURN_IF((NULL == pv_buf), IV_FAIL); 2033 memset(pv_buf, 0, size); 2034 ps_dec->ps_pred_pkd = pv_buf; 2035 2036 /* Allocate memory for coeff data */ 2037 size = MB_LUM_SIZE * sizeof(WORD16); 2038 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent 2039 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent 2040 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */ 2041 size += u4_total_mbs * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t)) 2042 + 9 * sizeof(tu_sblk4x4_coeff_data_t)); 2043 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data 2044 size += u4_total_mbs * 32; 2045 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2046 RETURN_IF((NULL == pv_buf), IV_FAIL); 2047 memset(pv_buf, 0, size); 2048 2049 ps_dec->pi2_coeff_data = pv_buf; 2050 2051 ps_dec->pv_pic_tu_coeff_data = (void *)(ps_dec->pi2_coeff_data + MB_LUM_SIZE); 2052 2053 /* Allocate MV bank buffer */ 2054 { 2055 UWORD32 col_flag_buffer_size, mvpred_buffer_size; 2056 2057 col_flag_buffer_size = ((ps_dec->u2_pic_wd * ps_dec->u2_pic_ht) >> 4); 2058 mvpred_buffer_size = sizeof(mv_pred_t) 2059 * ((ps_dec->u2_pic_wd * (ps_dec->u2_pic_ht + PAD_MV_BANK_ROW)) >> 4); 2060 2061 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2062 2063 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs); 2064 u4_num_bufs = MAX(u4_num_bufs, 2); 2065 size = ALIGN64(mvpred_buffer_size) + ALIGN64(col_flag_buffer_size); 2066 size *= u4_num_bufs; 2067 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2068 RETURN_IF((NULL == pv_buf), IV_FAIL); 2069 memset(pv_buf, 0, size); 2070 ps_dec->pu1_mv_bank_buf_base = pv_buf; 2071 } 2072 2073 /* Allocate Pic buffer */ 2074 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y; 2075 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv; 2076 2077 { 2078 if(ps_dec->u4_share_disp_buf == 1) 2079 { 2080 /* In case of buffers getting shared between application and library 2081 there is no need of reference memtabs. Instead of setting the i4_size 2082 to zero, it is reduced to a small i4_size to ensure that changes 2083 in the code are minimal */ 2084 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2085 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU) 2086 || (ps_dec->u1_chroma_format == IV_YUV_420P)) 2087 { 2088 u4_luma_size = 64; 2089 } 2090 2091 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2092 { 2093 u4_chroma_size = 64; 2094 } 2095 2096 } 2097 } 2098 2099 size = ALIGN64(u4_luma_size) + ALIGN64(u4_chroma_size); 2100 size *= ps_dec->u1_pic_bufs; 2101 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2102 RETURN_IF((NULL == pv_buf), IV_FAIL); 2103 memset(pv_buf, 0, size); 2104 ps_dec->pu1_pic_buf_base = pv_buf; 2105 2106 /* Post allocation Increment Actions */ 2107 2108 /***************************************************************************/ 2109 /*Initialize cabac context pointers for every SE that has fixed contextIdx */ 2110 /***************************************************************************/ 2111 { 2112 bin_ctxt_model_t * const p_cabac_ctxt_table_t = 2113 ps_dec->p_cabac_ctxt_table_t; 2114 bin_ctxt_model_t * * p_coeff_abs_level_minus1_t = 2115 ps_dec->p_coeff_abs_level_minus1_t; 2116 bin_ctxt_model_t * * p_cbf_t = ps_dec->p_cbf_t; 2117 2118 ps_dec->p_mb_field_dec_flag_t = p_cabac_ctxt_table_t 2119 + MB_FIELD_DECODING_FLAG; 2120 ps_dec->p_prev_intra4x4_pred_mode_flag_t = p_cabac_ctxt_table_t 2121 + PREV_INTRA4X4_PRED_MODE_FLAG; 2122 ps_dec->p_rem_intra4x4_pred_mode_t = p_cabac_ctxt_table_t 2123 + REM_INTRA4X4_PRED_MODE; 2124 ps_dec->p_intra_chroma_pred_mode_t = p_cabac_ctxt_table_t 2125 + INTRA_CHROMA_PRED_MODE; 2126 ps_dec->p_mb_qp_delta_t = p_cabac_ctxt_table_t + MB_QP_DELTA; 2127 ps_dec->p_ref_idx_t = p_cabac_ctxt_table_t + REF_IDX; 2128 ps_dec->p_mvd_x_t = p_cabac_ctxt_table_t + MVD_X; 2129 ps_dec->p_mvd_y_t = p_cabac_ctxt_table_t + MVD_Y; 2130 p_cbf_t[0] = p_cabac_ctxt_table_t + CBF + 0; 2131 p_cbf_t[1] = p_cabac_ctxt_table_t + CBF + 4; 2132 p_cbf_t[2] = p_cabac_ctxt_table_t + CBF + 8; 2133 p_cbf_t[3] = p_cabac_ctxt_table_t + CBF + 12; 2134 p_cbf_t[4] = p_cabac_ctxt_table_t + CBF + 16; 2135 ps_dec->p_cbp_luma_t = p_cabac_ctxt_table_t + CBP_LUMA; 2136 ps_dec->p_cbp_chroma_t = p_cabac_ctxt_table_t + CBP_CHROMA; 2137 2138 p_coeff_abs_level_minus1_t[LUMA_DC_CTXCAT] = p_cabac_ctxt_table_t 2139 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_0_OFFSET; 2140 2141 p_coeff_abs_level_minus1_t[LUMA_AC_CTXCAT] = p_cabac_ctxt_table_t 2142 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_1_OFFSET; 2143 2144 p_coeff_abs_level_minus1_t[LUMA_4X4_CTXCAT] = p_cabac_ctxt_table_t 2145 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_2_OFFSET; 2146 2147 p_coeff_abs_level_minus1_t[CHROMA_DC_CTXCAT] = p_cabac_ctxt_table_t 2148 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_3_OFFSET; 2149 2150 p_coeff_abs_level_minus1_t[CHROMA_AC_CTXCAT] = p_cabac_ctxt_table_t 2151 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_4_OFFSET; 2152 2153 p_coeff_abs_level_minus1_t[LUMA_8X8_CTXCAT] = p_cabac_ctxt_table_t 2154 + COEFF_ABS_LEVEL_MINUS1_8X8 2155 + COEFF_ABS_LEVEL_CAT_5_OFFSET; 2156 2157 /********************************************************/ 2158 /* context for the high profile related syntax elements */ 2159 /* This is maintained seperately in s_high_profile */ 2160 /********************************************************/ 2161 { 2162 2163 ps_dec->s_high_profile.ps_transform8x8_flag = p_cabac_ctxt_table_t 2164 + TRANSFORM_SIZE_8X8_FLAG; 2165 2166 ps_dec->s_high_profile.ps_sigcoeff_8x8_frame = p_cabac_ctxt_table_t 2167 + SIGNIFICANT_COEFF_FLAG_8X8_FRAME; 2168 2169 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_frame = 2170 p_cabac_ctxt_table_t 2171 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FRAME; 2172 2173 ps_dec->s_high_profile.ps_coeff_abs_levelminus1 = 2174 p_cabac_ctxt_table_t + COEFF_ABS_LEVEL_MINUS1_8X8; 2175 2176 ps_dec->s_high_profile.ps_sigcoeff_8x8_field = p_cabac_ctxt_table_t 2177 + SIGNIFICANT_COEFF_FLAG_8X8_FIELD; 2178 2179 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_field = 2180 p_cabac_ctxt_table_t 2181 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FIELD; 2182 } 2183 } 2184 return (i16_status); 2185 } 2186 2187 /*! 2188 ************************************************************************** 2189 * \if Function name : ih264d_free_dynamic_bufs \endif 2190 * 2191 * \brief 2192 * This function frees dynamic memory allocated by Decoder. 2193 * 2194 * \param ps_dec: Pointer to dec_struct_t. 2195 * 2196 * \return 2197 * Returns i4_status as returned by MemManager. 2198 * 2199 ************************************************************************** 2200 */ 2201 WORD16 ih264d_free_dynamic_bufs(dec_struct_t * ps_dec) 2202 { 2203 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_dynamic); 2204 2205 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_pic); 2206 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_dec_mb_map); 2207 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_recon_mb_map); 2208 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu2_slice_num_map); 2209 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_slice_buf); 2210 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_frm_mb_info); 2211 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_coeff_data); 2212 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_mb_data); 2213 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_part_params); 2214 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_top_mb); 2215 2216 if(ps_dec->p_ctxt_inc_mb_map) 2217 { 2218 ps_dec->p_ctxt_inc_mb_map -= 1; 2219 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_ctxt_inc_mb_map); 2220 } 2221 2222 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[0]); 2223 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[1]); 2224 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred_pkd); 2225 { 2226 UWORD8 i; 2227 for(i = 0; i < MV_SCRATCH_BUFS; i++) 2228 { 2229 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_top_p[i]); 2230 } 2231 } 2232 2233 if(ps_dec->pu1_y_intra_pred_line) 2234 { 2235 ps_dec->pu1_y_intra_pred_line -= MB_SIZE; 2236 } 2237 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_y_intra_pred_line); 2238 2239 if(ps_dec->pu1_u_intra_pred_line) 2240 { 2241 ps_dec->pu1_u_intra_pred_line -= MB_SIZE; 2242 } 2243 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_u_intra_pred_line); 2244 2245 if(ps_dec->pu1_v_intra_pred_line) 2246 { 2247 ps_dec->pu1_v_intra_pred_line -= MB_SIZE; 2248 } 2249 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_v_intra_pred_line); 2250 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_nbr_mb_row); 2251 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_mv_bank_buf_base); 2252 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_pic_buf_base); 2253 return 0; 2254 } 2255 2256 /*! 2257 ************************************************************************** 2258 * \if Function name : ih264d_create_mv_bank \endif 2259 * 2260 * \brief 2261 * This function creates MV bank. 2262 * 2263 * \param memType : Type of memory being handled 2264 * 0: Display Buffer 2265 * 1: Decoder Buffer 2266 * 2: Internal Buffer 2267 * \param u1_num_of_buf: Number of decode or display buffers. 2268 * \param u4_wd : Frame width. 2269 * \param u4_ht : Frame Height. 2270 * \param ps_pic_buf_api : Pointer to Picture Buffer API. 2271 * \param ih264d_dec_mem_manager : Memory manager utility supplied by system. 2272 * 2273 * \return 2274 * 0 on Success and -1 on error 2275 * 2276 ************************************************************************** 2277 */ 2278 WORD32 ih264d_create_mv_bank(void *pv_dec, 2279 UWORD32 ui_width, 2280 UWORD32 ui_height) 2281 { 2282 UWORD8 i; 2283 UWORD32 col_flag_buffer_size, mvpred_buffer_size; 2284 UWORD8 *pu1_mv_buf_mgr_base, *pu1_mv_bank_base; 2285 col_mv_buf_t *ps_col_mv; 2286 mv_pred_t *ps_mv; 2287 UWORD8 *pu1_col_zero_flag_buf; 2288 dec_struct_t *ps_dec = (dec_struct_t *)pv_dec; 2289 WORD32 buf_ret; 2290 UWORD32 u4_num_bufs; 2291 UWORD8 *pu1_buf; 2292 WORD32 size; 2293 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 2294 2295 col_flag_buffer_size = ((ui_width * ui_height) >> 4); 2296 mvpred_buffer_size = sizeof(mv_pred_t) 2297 * ((ui_width * (ui_height + PAD_MV_BANK_ROW)) >> 4); 2298 2299 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_mv_buf_mgr); 2300 2301 ps_col_mv = ps_dec->ps_col_mv_base; 2302 2303 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2304 2305 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs); 2306 u4_num_bufs = MAX(u4_num_bufs, 2); 2307 pu1_buf = ps_dec->pu1_mv_bank_buf_base; 2308 for(i = 0 ; i < u4_num_bufs ; i++) 2309 { 2310 pu1_col_zero_flag_buf = pu1_buf; 2311 pu1_buf += ALIGN64(col_flag_buffer_size); 2312 2313 ps_mv = (mv_pred_t *)pu1_buf; 2314 pu1_buf += ALIGN64(mvpred_buffer_size); 2315 2316 memset(ps_mv, 0, ((ui_width * OFFSET_MV_BANK_ROW) >> 4) * sizeof(mv_pred_t)); 2317 ps_mv += (ui_width*OFFSET_MV_BANK_ROW) >> 4; 2318 2319 ps_col_mv->pv_col_zero_flag = (void *)pu1_col_zero_flag_buf; 2320 ps_col_mv->pv_mv = (void *)ps_mv; 2321 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_mv_buf_mgr, ps_col_mv, i); 2322 if(0 != buf_ret) 2323 { 2324 ps_dec->i4_error_code = ERROR_BUF_MGR; 2325 return ERROR_BUF_MGR; 2326 } 2327 ps_col_mv++; 2328 } 2329 return OK; 2330 } 2331 2332 void ih264d_unpack_coeff4x4_dc_4x4blk(tu_sblk4x4_coeff_data_t *ps_tu_4x4, 2333 WORD16 *pi2_out_coeff_data, 2334 UWORD8 *pu1_inv_scan) 2335 { 2336 UWORD16 u2_sig_coeff_map = ps_tu_4x4->u2_sig_coeff_map; 2337 WORD32 idx; 2338 WORD16 *pi2_coeff_data = &ps_tu_4x4->ai2_level[0]; 2339 2340 while(u2_sig_coeff_map) 2341 { 2342 idx = CLZ(u2_sig_coeff_map); 2343 2344 idx = 31 - idx; 2345 RESET_BIT(u2_sig_coeff_map,idx); 2346 2347 idx = pu1_inv_scan[idx]; 2348 pi2_out_coeff_data[idx] = *pi2_coeff_data++; 2349 2350 } 2351 } 2352
