1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2006 Freescale Semiconductor, Inc. 4 * 5 * Dave Liu <daveliu (at) freescale.com> 6 * based on source code of Shlomi Gridish 7 */ 8 9 #ifndef __UCCF_H__ 10 #define __UCCF_H__ 11 12 #include "common.h" 13 #include "linux/immap_qe.h" 14 #include <fsl_qe.h> 15 16 /* Fast or Giga ethernet 17 */ 18 typedef enum enet_type { 19 FAST_ETH, 20 GIGA_ETH, 21 } enet_type_e; 22 23 /* General UCC Extended Mode Register 24 */ 25 #define UCC_GUEMR_MODE_MASK_RX 0x02 26 #define UCC_GUEMR_MODE_MASK_TX 0x01 27 #define UCC_GUEMR_MODE_FAST_RX 0x02 28 #define UCC_GUEMR_MODE_FAST_TX 0x01 29 #define UCC_GUEMR_MODE_SLOW_RX 0x00 30 #define UCC_GUEMR_MODE_SLOW_TX 0x00 31 #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 must be set 1 */ 32 33 /* General UCC FAST Mode Register 34 */ 35 #define UCC_FAST_GUMR_TCI 0x20000000 36 #define UCC_FAST_GUMR_TRX 0x10000000 37 #define UCC_FAST_GUMR_TTX 0x08000000 38 #define UCC_FAST_GUMR_CDP 0x04000000 39 #define UCC_FAST_GUMR_CTSP 0x02000000 40 #define UCC_FAST_GUMR_CDS 0x01000000 41 #define UCC_FAST_GUMR_CTSS 0x00800000 42 #define UCC_FAST_GUMR_TXSY 0x00020000 43 #define UCC_FAST_GUMR_RSYN 0x00010000 44 #define UCC_FAST_GUMR_RTSM 0x00002000 45 #define UCC_FAST_GUMR_REVD 0x00000400 46 #define UCC_FAST_GUMR_ENR 0x00000020 47 #define UCC_FAST_GUMR_ENT 0x00000010 48 49 /* GUMR [MODE] bit maps 50 */ 51 #define UCC_FAST_GUMR_HDLC 0x00000000 52 #define UCC_FAST_GUMR_QMC 0x00000002 53 #define UCC_FAST_GUMR_UART 0x00000004 54 #define UCC_FAST_GUMR_BISYNC 0x00000008 55 #define UCC_FAST_GUMR_ATM 0x0000000a 56 #define UCC_FAST_GUMR_ETH 0x0000000c 57 58 /* Transmit On Demand (UTORD) 59 */ 60 #define UCC_SLOW_TOD 0x8000 61 #define UCC_FAST_TOD 0x8000 62 63 /* Fast Ethernet (10/100 Mbps) 64 */ 65 #define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size */ 66 #define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */ 67 #define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */ 68 #define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size */ 69 #define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */ 70 #define UCC_GETH_UTFTT_INIT 128 71 72 /* Gigabit Ethernet (1000 Mbps) 73 */ 74 #define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual FIFO size */ 75 #define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */ 76 #define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */ 77 #define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual FIFO size */ 78 #define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */ 79 #define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */ 80 81 /* UCC fast alignment 82 */ 83 #define UCC_FAST_RX_ALIGN 4 84 #define UCC_FAST_MRBLR_ALIGNMENT 4 85 #define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8 86 87 /* Sizes 88 */ 89 #define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8 90 91 /* UCC fast structure. 92 */ 93 typedef struct ucc_fast_info { 94 int ucc_num; 95 qe_clock_e rx_clock; 96 qe_clock_e tx_clock; 97 enet_type_e eth_type; 98 } ucc_fast_info_t; 99 100 typedef struct ucc_fast_private { 101 ucc_fast_info_t *uf_info; 102 ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */ 103 u32 *p_ucce; /* a pointer to the event register */ 104 u32 *p_uccm; /* a pointer to the mask register */ 105 int enabled_tx; /* whether UCC is enabled for Tx (ENT) */ 106 int enabled_rx; /* whether UCC is enabled for Rx (ENR) */ 107 u32 ucc_fast_tx_virtual_fifo_base_offset; 108 u32 ucc_fast_rx_virtual_fifo_base_offset; 109 } ucc_fast_private_t; 110 111 void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf); 112 u32 ucc_fast_get_qe_cr_subblock(int ucc_num); 113 void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode); 114 void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode); 115 int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret); 116 117 #endif /* __UCCF_H__ */ 118
