| /external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-objdump/ARM/ |
| v7m-subarch.s | 5 umlal: label
6 umlal r0, r1, r2, r3 label
8 @ CHECK-LABEL: umlal
9 @ CHECK: e2 fb 03 01 umlal r0, r1, r2, r3
|
| /external/llvm/test/MC/ARM/ |
| mul-v4.s | 1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
32 @ ARMV4: umlal r2, r3, r0, r1 @ encoding: [0x90,0x21,0xa3,0xe0]
36 umlal r2,r3,r0,r1 label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| mul-v4.s | 1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
32 @ ARMV4: umlal r2, r3, r0, r1 @ encoding: [0x90,0x21,0xa3,0xe0]
36 umlal r2,r3,r0,r1 label
|
| /external/v8/src/arm64/ |
| simulator-logic-arm64.cc | 790 LogicVRegister Simulator::umlal(VectorFormat vform, LogicVRegister dst, function in class:v8::internal::Simulator
796 return umlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
2634 LogicVRegister Simulator::umlal(VectorFormat vform, LogicVRegister dst, function in class:v8::internal::Simulator
[all...] |
| /external/vixl/src/aarch64/ |
| logic-aarch64.cc | 729 LogicVRegister Simulator::umlal(VectorFormat vform, function in class:vixl::aarch64::Simulator
737 return umlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
3226 LogicVRegister Simulator::umlal(VectorFormat vform, function in class:vixl::aarch64::Simulator
[all...] |
| /external/v8/src/arm/ |
| assembler-arm.cc | 1771 void Assembler::umlal(Register dstL, function in class:v8::internal::Assembler
[all...] |
| /external/vixl/src/aarch32/ |
| assembler-aarch32.cc | 13227 void Assembler::umlal( function in class:vixl::aarch32::Assembler
[all...] |
| assembler-aarch32.h | 3668 void umlal(Register rdlo, Register rdhi, Register rn, Register rm) { function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.cc | 3469 void Disassembler::umlal( function in class:vixl::aarch32::Disassembler
[all...] |
