1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * atmel_lcd.h - Atmel LCD Controller structures 4 * 5 * (C) Copyright 2001 6 * Wolfgang Denk, DENX Software Engineering, wd (at) denx.de. 7 */ 8 9 #ifndef _ATMEL_LCD_H_ 10 #define _ATMEL_LCD_H_ 11 12 /** 13 * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model 14 * 15 * @timing_index: Index of LCD timing to use in device tree node 16 */ 17 struct atmel_lcd_platdata { 18 int timing_index; 19 }; 20 21 typedef struct vidinfo { 22 ushort vl_col; /* Number of columns (i.e. 640) */ 23 ushort vl_row; /* Number of rows (i.e. 480) */ 24 ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ 25 u_long vl_clk; /* pixel clock in ps */ 26 27 /* LCD configuration register */ 28 u_long vl_sync; /* Horizontal / vertical sync */ 29 u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 30 u_long vl_tft; /* 0 = passive, 1 = TFT */ 31 u_long vl_cont_pol_low; /* contrast polarity is low */ 32 u_long vl_clk_pol; /* clock polarity */ 33 34 /* Horizontal control register. */ 35 u_long vl_hsync_len; /* Length of horizontal sync */ 36 u_long vl_left_margin; /* Time from sync to picture */ 37 u_long vl_right_margin; /* Time from picture to sync */ 38 39 /* Vertical control register. */ 40 u_long vl_vsync_len; /* Length of vertical sync */ 41 u_long vl_upper_margin; /* Time from sync to picture */ 42 u_long vl_lower_margin; /* Time from picture to sync */ 43 44 u_long mmio; /* Memory mapped registers */ 45 46 u_int logo_width; 47 u_int logo_height; 48 int logo_x_offset; 49 int logo_y_offset; 50 u_long logo_addr; 51 } vidinfo_t; 52 53 void atmel_logo_info(vidinfo_t *info); 54 void microchip_logo_info(vidinfo_t *info); 55 56 #endif 57
