1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012 Samsung Electronics 4 * R. Chandrasekar <rcsekar (at) samsung.com> 5 */ 6 #include <common.h> 7 #include <asm/arch/clk.h> 8 #include <asm/arch/cpu.h> 9 #include <asm/gpio.h> 10 #include <asm/io.h> 11 #include <div64.h> 12 #include <fdtdec.h> 13 #include <i2c.h> 14 #include <i2s.h> 15 #include <sound.h> 16 #include <asm/arch/sound.h> 17 #include "wm8994.h" 18 #include "wm8994_registers.h" 19 20 /* defines for wm8994 system clock selection */ 21 #define SEL_MCLK1 0x00 22 #define SEL_MCLK2 0x08 23 #define SEL_FLL1 0x10 24 #define SEL_FLL2 0x18 25 26 /* fll config to configure fll */ 27 struct wm8994_fll_config { 28 int src; /* Source */ 29 int in; /* Input frequency in Hz */ 30 int out; /* output frequency in Hz */ 31 }; 32 33 /* codec private data */ 34 struct wm8994_priv { 35 enum wm8994_type type; /* codec type of wolfson */ 36 int revision; /* Revision */ 37 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */ 38 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */ 39 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */ 40 struct wm8994_fll_config fll[2]; /* fll config to configure fll */ 41 }; 42 43 /* wm 8994 supported sampling rate values */ 44 static unsigned int src_rate[] = { 45 8000, 11025, 12000, 16000, 22050, 24000, 46 32000, 44100, 48000, 88200, 96000 47 }; 48 49 /* op clock divisions */ 50 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 51 52 /* lr clock frame size ratio */ 53 static int fs_ratios[] = { 54 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 55 }; 56 57 /* bit clock divisors */ 58 static int bclk_divs[] = { 59 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 60 640, 880, 960, 1280, 1760, 1920 61 }; 62 63 static struct wm8994_priv g_wm8994_info; 64 static unsigned char g_wm8994_i2c_dev_addr; 65 static struct sound_codec_info g_codec_info; 66 67 /* 68 * Initialise I2C for wm 8994 69 * 70 * @param bus no i2c bus number in which wm8994 is connected 71 */ 72 static void wm8994_i2c_init(int bus_no) 73 { 74 i2c_set_bus_num(bus_no); 75 } 76 77 /* 78 * Writes value to a device register through i2c 79 * 80 * @param reg reg number to be write 81 * @param data data to be writen to the above registor 82 * 83 * @return int value 1 for change, 0 for no change or negative error code. 84 */ 85 static int wm8994_i2c_write(unsigned int reg, unsigned short data) 86 { 87 unsigned char val[2]; 88 89 val[0] = (unsigned char)((data >> 8) & 0xff); 90 val[1] = (unsigned char)(data & 0xff); 91 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data); 92 93 return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2); 94 } 95 96 /* 97 * Read a value from a device register through i2c 98 * 99 * @param reg reg number to be read 100 * @param data address of read data to be stored 101 * 102 * @return int value 0 for success, -1 in case of error. 103 */ 104 static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data) 105 { 106 unsigned char val[2]; 107 int ret; 108 109 ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2); 110 if (ret != 0) { 111 debug("%s: Error while reading register %#04x\n", 112 __func__, reg); 113 return -1; 114 } 115 116 *data = val[0]; 117 *data <<= 8; 118 *data |= val[1]; 119 120 return 0; 121 } 122 123 /* 124 * update device register bits through i2c 125 * 126 * @param reg codec register 127 * @param mask register mask 128 * @param value new value 129 * 130 * @return int value 1 if change in the register value, 131 * 0 for no change or negative error code. 132 */ 133 static int wm8994_update_bits(unsigned int reg, unsigned short mask, 134 unsigned short value) 135 { 136 int change , ret = 0; 137 unsigned short old, new; 138 139 if (wm8994_i2c_read(reg, &old) != 0) 140 return -1; 141 new = (old & ~mask) | (value & mask); 142 change = (old != new) ? 1 : 0; 143 if (change) 144 ret = wm8994_i2c_write(reg, new); 145 if (ret < 0) 146 return ret; 147 148 return change; 149 } 150 151 /* 152 * Sets i2s set format 153 * 154 * @param aif_id Interface ID 155 * @param fmt i2S format 156 * 157 * @return -1 for error and 0 Success. 158 */ 159 int wm8994_set_fmt(int aif_id, unsigned int fmt) 160 { 161 int ms_reg; 162 int aif_reg; 163 int ms = 0; 164 int aif = 0; 165 int aif_clk = 0; 166 int error = 0; 167 168 switch (aif_id) { 169 case 1: 170 ms_reg = WM8994_AIF1_MASTER_SLAVE; 171 aif_reg = WM8994_AIF1_CONTROL_1; 172 aif_clk = WM8994_AIF1_CLOCKING_1; 173 break; 174 case 2: 175 ms_reg = WM8994_AIF2_MASTER_SLAVE; 176 aif_reg = WM8994_AIF2_CONTROL_1; 177 aif_clk = WM8994_AIF2_CLOCKING_1; 178 break; 179 default: 180 debug("%s: Invalid audio interface selection\n", __func__); 181 return -1; 182 } 183 184 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 185 case SND_SOC_DAIFMT_CBS_CFS: 186 break; 187 case SND_SOC_DAIFMT_CBM_CFM: 188 ms = WM8994_AIF1_MSTR; 189 break; 190 default: 191 debug("%s: Invalid i2s master selection\n", __func__); 192 return -1; 193 } 194 195 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 196 case SND_SOC_DAIFMT_DSP_B: 197 aif |= WM8994_AIF1_LRCLK_INV; 198 case SND_SOC_DAIFMT_DSP_A: 199 aif |= 0x18; 200 break; 201 case SND_SOC_DAIFMT_I2S: 202 aif |= 0x10; 203 break; 204 case SND_SOC_DAIFMT_RIGHT_J: 205 break; 206 case SND_SOC_DAIFMT_LEFT_J: 207 aif |= 0x8; 208 break; 209 default: 210 debug("%s: Invalid i2s format selection\n", __func__); 211 return -1; 212 } 213 214 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 215 case SND_SOC_DAIFMT_DSP_A: 216 case SND_SOC_DAIFMT_DSP_B: 217 /* frame inversion not valid for DSP modes */ 218 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 219 case SND_SOC_DAIFMT_NB_NF: 220 break; 221 case SND_SOC_DAIFMT_IB_NF: 222 aif |= WM8994_AIF1_BCLK_INV; 223 break; 224 default: 225 debug("%s: Invalid i2s frame inverse selection\n", 226 __func__); 227 return -1; 228 } 229 break; 230 231 case SND_SOC_DAIFMT_I2S: 232 case SND_SOC_DAIFMT_RIGHT_J: 233 case SND_SOC_DAIFMT_LEFT_J: 234 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 235 case SND_SOC_DAIFMT_NB_NF: 236 break; 237 case SND_SOC_DAIFMT_IB_IF: 238 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 239 break; 240 case SND_SOC_DAIFMT_IB_NF: 241 aif |= WM8994_AIF1_BCLK_INV; 242 break; 243 case SND_SOC_DAIFMT_NB_IF: 244 aif |= WM8994_AIF1_LRCLK_INV; 245 break; 246 default: 247 debug("%s: Invalid i2s clock polarity selection\n", 248 __func__); 249 return -1; 250 } 251 break; 252 default: 253 debug("%s: Invalid i2s format selection\n", __func__); 254 return -1; 255 } 256 257 error = wm8994_update_bits(aif_reg, WM8994_AIF1_BCLK_INV | 258 WM8994_AIF1_LRCLK_INV_MASK | WM8994_AIF1_FMT_MASK, aif); 259 260 error |= wm8994_update_bits(ms_reg, WM8994_AIF1_MSTR_MASK, ms); 261 error |= wm8994_update_bits(aif_clk, WM8994_AIF1CLK_ENA_MASK, 262 WM8994_AIF1CLK_ENA); 263 if (error < 0) { 264 debug("%s: codec register access error\n", __func__); 265 return -1; 266 } 267 268 return 0; 269 } 270 271 /* 272 * Sets hw params FOR WM8994 273 * 274 * @param wm8994 wm8994 information pointer 275 * @param aif_id Audio interface ID 276 * @param sampling_rate Sampling rate 277 * @param bits_per_sample Bits per sample 278 * @param Channels Channels in the given audio input 279 * 280 * @return -1 for error and 0 Success. 281 */ 282 static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id, 283 unsigned int sampling_rate, unsigned int bits_per_sample, 284 unsigned int channels) 285 { 286 int aif1_reg; 287 int aif2_reg; 288 int bclk_reg; 289 int bclk = 0; 290 int rate_reg; 291 int aif1 = 0; 292 int aif2 = 0; 293 int rate_val = 0; 294 int id = aif_id - 1; 295 int i, cur_val, best_val, bclk_rate, best; 296 unsigned short reg_data; 297 int ret = 0; 298 299 switch (aif_id) { 300 case 1: 301 aif1_reg = WM8994_AIF1_CONTROL_1; 302 aif2_reg = WM8994_AIF1_CONTROL_2; 303 bclk_reg = WM8994_AIF1_BCLK; 304 rate_reg = WM8994_AIF1_RATE; 305 break; 306 case 2: 307 aif1_reg = WM8994_AIF2_CONTROL_1; 308 aif2_reg = WM8994_AIF2_CONTROL_2; 309 bclk_reg = WM8994_AIF2_BCLK; 310 rate_reg = WM8994_AIF2_RATE; 311 break; 312 default: 313 return -1; 314 } 315 316 bclk_rate = sampling_rate * 32; 317 switch (bits_per_sample) { 318 case 16: 319 bclk_rate *= 16; 320 break; 321 case 20: 322 bclk_rate *= 20; 323 aif1 |= 0x20; 324 break; 325 case 24: 326 bclk_rate *= 24; 327 aif1 |= 0x40; 328 break; 329 case 32: 330 bclk_rate *= 32; 331 aif1 |= 0x60; 332 break; 333 default: 334 return -1; 335 } 336 337 /* Try to find an appropriate sample rate; look for an exact match. */ 338 for (i = 0; i < ARRAY_SIZE(src_rate); i++) 339 if (src_rate[i] == sampling_rate) 340 break; 341 342 if (i == ARRAY_SIZE(src_rate)) { 343 debug("%s: Could not get the best matching samplingrate\n", 344 __func__); 345 return -1; 346 } 347 348 rate_val |= i << WM8994_AIF1_SR_SHIFT; 349 350 /* AIFCLK/fs ratio; look for a close match in either direction */ 351 best = 0; 352 best_val = abs((fs_ratios[0] * sampling_rate) 353 - wm8994->aifclk[id]); 354 355 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 356 cur_val = abs((fs_ratios[i] * sampling_rate) 357 - wm8994->aifclk[id]); 358 if (cur_val >= best_val) 359 continue; 360 best = i; 361 best_val = cur_val; 362 } 363 364 rate_val |= best; 365 366 /* 367 * We may not get quite the right frequency if using 368 * approximate clocks so look for the closest match that is 369 * higher than the target (we need to ensure that there enough 370 * BCLKs to clock out the samples). 371 */ 372 best = 0; 373 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 374 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 375 if (cur_val < 0) /* BCLK table is sorted */ 376 break; 377 best = i; 378 } 379 380 if (i == ARRAY_SIZE(bclk_divs)) { 381 debug("%s: Could not get the best matching bclk division\n", 382 __func__); 383 return -1; 384 } 385 386 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 387 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 388 389 if (wm8994_i2c_read(aif1_reg, ®_data) != 0) { 390 debug("%s: AIF1 register read Failed\n", __func__); 391 return -1; 392 } 393 394 if ((channels == 1) && ((reg_data & 0x18) == 0x18)) 395 aif2 |= WM8994_AIF1_MONO; 396 397 if (wm8994->aifclk[id] == 0) { 398 debug("%s:Audio interface clock not set\n", __func__); 399 return -1; 400 } 401 402 ret = wm8994_update_bits(aif1_reg, WM8994_AIF1_WL_MASK, aif1); 403 ret |= wm8994_update_bits(aif2_reg, WM8994_AIF1_MONO, aif2); 404 ret |= wm8994_update_bits(bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 405 ret |= wm8994_update_bits(rate_reg, WM8994_AIF1_SR_MASK | 406 WM8994_AIF1CLK_RATE_MASK, rate_val); 407 408 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk); 409 410 if (ret < 0) { 411 debug("%s: codec register access error\n", __func__); 412 return -1; 413 } 414 415 return 0; 416 } 417 418 /* 419 * Configures Audio interface Clock 420 * 421 * @param wm8994 wm8994 information pointer 422 * @param aif Audio Interface ID 423 * 424 * @return -1 for error and 0 Success. 425 */ 426 static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) 427 { 428 int rate; 429 int reg1 = 0; 430 int offset; 431 int ret; 432 433 /* AIF(1/0) register adress offset calculated */ 434 if (aif-1) 435 offset = 4; 436 else 437 offset = 0; 438 439 switch (wm8994->sysclk[aif-1]) { 440 case WM8994_SYSCLK_MCLK1: 441 reg1 |= SEL_MCLK1; 442 rate = wm8994->mclk[0]; 443 break; 444 445 case WM8994_SYSCLK_MCLK2: 446 reg1 |= SEL_MCLK2; 447 rate = wm8994->mclk[1]; 448 break; 449 450 case WM8994_SYSCLK_FLL1: 451 reg1 |= SEL_FLL1; 452 rate = wm8994->fll[0].out; 453 break; 454 455 case WM8994_SYSCLK_FLL2: 456 reg1 |= SEL_FLL2; 457 rate = wm8994->fll[1].out; 458 break; 459 460 default: 461 debug("%s: Invalid input clock selection [%d]\n", 462 __func__, wm8994->sysclk[aif-1]); 463 return -1; 464 } 465 466 /* if input clock frequenct is more than 135Mhz then divide */ 467 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) { 468 rate /= 2; 469 reg1 |= WM8994_AIF1CLK_DIV; 470 } 471 472 wm8994->aifclk[aif-1] = rate; 473 474 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset, 475 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 476 reg1); 477 478 if (aif == WM8994_AIF1) 479 ret |= wm8994_update_bits(WM8994_CLOCKING_1, 480 WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK, 481 WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); 482 else if (aif == WM8994_AIF2) 483 ret |= wm8994_update_bits(WM8994_CLOCKING_1, 484 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK | 485 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC | 486 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); 487 488 if (ret < 0) { 489 debug("%s: codec register access error\n", __func__); 490 return -1; 491 } 492 493 return 0; 494 } 495 496 /* 497 * Configures Audio interface for the given frequency 498 * 499 * @param wm8994 wm8994 information 500 * @param aif_id Audio Interface 501 * @param clk_id Input Clock ID 502 * @param freq Sampling frequency in Hz 503 * 504 * @return -1 for error and 0 success. 505 */ 506 static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, 507 int clk_id, unsigned int freq) 508 { 509 int i; 510 int ret = 0; 511 512 wm8994->sysclk[aif_id - 1] = clk_id; 513 514 switch (clk_id) { 515 case WM8994_SYSCLK_MCLK1: 516 wm8994->mclk[0] = freq; 517 if (aif_id == 2) { 518 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_2 , 519 WM8994_AIF2DAC_DIV_MASK , 0); 520 } 521 break; 522 523 case WM8994_SYSCLK_MCLK2: 524 /* TODO: Set GPIO AF */ 525 wm8994->mclk[1] = freq; 526 break; 527 528 case WM8994_SYSCLK_FLL1: 529 case WM8994_SYSCLK_FLL2: 530 break; 531 532 case WM8994_SYSCLK_OPCLK: 533 /* 534 * Special case - a division (times 10) is given and 535 * no effect on main clocking. 536 */ 537 if (freq) { 538 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 539 if (opclk_divs[i] == freq) 540 break; 541 if (i == ARRAY_SIZE(opclk_divs)) { 542 debug("%s frequency divisor not found\n", 543 __func__); 544 return -1; 545 } 546 ret = wm8994_update_bits(WM8994_CLOCKING_2, 547 WM8994_OPCLK_DIV_MASK, i); 548 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2, 549 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 550 } else { 551 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2, 552 WM8994_OPCLK_ENA, 0); 553 } 554 555 default: 556 debug("%s Invalid input clock selection [%d]\n", 557 __func__, clk_id); 558 return -1; 559 } 560 561 ret |= configure_aif_clock(wm8994, aif_id); 562 563 if (ret < 0) { 564 debug("%s: codec register access error\n", __func__); 565 return -1; 566 } 567 568 return 0; 569 } 570 571 /* 572 * Initializes Volume for AIF2 to HP path 573 * 574 * @returns -1 for error and 0 Success. 575 * 576 */ 577 static int wm8994_init_volume_aif2_dac1(void) 578 { 579 int ret; 580 581 /* Unmute AIF2DAC */ 582 ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1, 583 WM8994_AIF2DAC_MUTE_MASK, 0); 584 585 586 ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME, 587 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK, 588 WM8994_AIF2DAC_VU | 0xff); 589 590 ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME, 591 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK, 592 WM8994_AIF2DAC_VU | 0xff); 593 594 595 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME, 596 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | 597 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 598 599 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME, 600 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | 601 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 602 /* Head Phone Volume */ 603 ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D); 604 ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); 605 606 if (ret < 0) { 607 debug("%s: codec register access error\n", __func__); 608 return -1; 609 } 610 611 return 0; 612 } 613 614 /* 615 * Initializes Volume for AIF1 to HP path 616 * 617 * @returns -1 for error and 0 Success. 618 * 619 */ 620 static int wm8994_init_volume_aif1_dac1(void) 621 { 622 int ret = 0; 623 624 /* Unmute AIF1DAC */ 625 ret |= wm8994_i2c_write(WM8994_AIF1_DAC_FILTERS_1, 0x0000); 626 627 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME, 628 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | 629 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 630 631 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME, 632 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | 633 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 634 /* Head Phone Volume */ 635 ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D); 636 ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); 637 638 if (ret < 0) { 639 debug("%s: codec register access error\n", __func__); 640 return -1; 641 } 642 643 return 0; 644 } 645 646 /* 647 * Intialise wm8994 codec device 648 * 649 * @param wm8994 wm8994 information 650 * 651 * @returns -1 for error and 0 Success. 652 */ 653 static int wm8994_device_init(struct wm8994_priv *wm8994, 654 enum en_audio_interface aif_id) 655 { 656 const char *devname; 657 unsigned short reg_data; 658 int ret; 659 660 wm8994_i2c_write(WM8994_SOFTWARE_RESET, WM8994_SW_RESET);/* Reset */ 661 662 ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, ®_data); 663 if (ret < 0) { 664 debug("Failed to read ID register\n"); 665 goto err; 666 } 667 668 if (reg_data == WM8994_ID) { 669 devname = "WM8994"; 670 debug("Device registered as type %d\n", wm8994->type); 671 wm8994->type = WM8994; 672 } else { 673 debug("Device is not a WM8994, ID is %x\n", ret); 674 ret = -1; 675 goto err; 676 } 677 678 ret = wm8994_i2c_read(WM8994_CHIP_REVISION, ®_data); 679 if (ret < 0) { 680 debug("Failed to read revision register: %d\n", ret); 681 goto err; 682 } 683 wm8994->revision = reg_data; 684 debug("%s revision %c\n", devname, 'A' + wm8994->revision); 685 686 /* VMID Selection */ 687 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 688 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3); 689 690 /* Charge Pump Enable */ 691 ret |= wm8994_update_bits(WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK, 692 WM8994_CP_ENA); 693 694 /* Head Phone Power Enable */ 695 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 696 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA); 697 698 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 699 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA); 700 701 if (aif_id == WM8994_AIF1) { 702 ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_2, 703 WM8994_TSHUT_ENA | WM8994_MIXINL_ENA | 704 WM8994_MIXINR_ENA | WM8994_IN2L_ENA | 705 WM8994_IN2R_ENA); 706 707 ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_4, 708 WM8994_ADCL_ENA | WM8994_ADCR_ENA | 709 WM8994_AIF1ADC1R_ENA | 710 WM8994_AIF1ADC1L_ENA); 711 712 /* Power enable for AIF1 and DAC1 */ 713 ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_5, 714 WM8994_AIF1DACL_ENA | 715 WM8994_AIF1DACR_ENA | 716 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA); 717 } else if (aif_id == WM8994_AIF2) { 718 /* Power enable for AIF2 and DAC1 */ 719 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5, 720 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK | 721 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK, 722 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | 723 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA); 724 } 725 /* Head Phone Initialisation */ 726 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, 727 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK, 728 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY); 729 730 ret |= wm8994_update_bits(WM8994_DC_SERVO_1, 731 WM8994_DCS_ENA_CHAN_0_MASK | 732 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 | 733 WM8994_DCS_ENA_CHAN_1); 734 735 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, 736 WM8994_HPOUT1L_DLY_MASK | 737 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK | 738 WM8994_HPOUT1R_OUTP_MASK | 739 WM8994_HPOUT1L_RMV_SHORT_MASK | 740 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY | 741 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP | 742 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT | 743 WM8994_HPOUT1R_RMV_SHORT); 744 745 /* MIXER Config DAC1 to HP */ 746 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_1, 747 WM8994_DAC1L_TO_HPOUT1L_MASK, WM8994_DAC1L_TO_HPOUT1L); 748 749 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2, 750 WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R); 751 752 if (aif_id == WM8994_AIF1) { 753 /* Routing AIF1 to DAC1 */ 754 ret |= wm8994_i2c_write(WM8994_DAC1_LEFT_MIXER_ROUTING, 755 WM8994_AIF1DAC1L_TO_DAC1L); 756 757 ret |= wm8994_i2c_write(WM8994_DAC1_RIGHT_MIXER_ROUTING, 758 WM8994_AIF1DAC1R_TO_DAC1R); 759 760 /* GPIO Settings for AIF1 */ 761 ret |= wm8994_i2c_write(WM8994_GPIO_1, WM8994_GPIO_DIR_OUTPUT 762 | WM8994_GPIO_FUNCTION_I2S_CLK 763 | WM8994_GPIO_INPUT_DEBOUNCE); 764 765 ret |= wm8994_init_volume_aif1_dac1(); 766 } else if (aif_id == WM8994_AIF2) { 767 /* Routing AIF2 to DAC1 */ 768 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING, 769 WM8994_AIF2DACL_TO_DAC1L_MASK, 770 WM8994_AIF2DACL_TO_DAC1L); 771 772 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING, 773 WM8994_AIF2DACR_TO_DAC1R_MASK, 774 WM8994_AIF2DACR_TO_DAC1R); 775 776 /* GPIO Settings for AIF2 */ 777 /* B CLK */ 778 ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK | 779 WM8994_GPIO_FUNCTION_MASK , 780 WM8994_GPIO_DIR_OUTPUT); 781 782 /* LR CLK */ 783 ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK | 784 WM8994_GPIO_FUNCTION_MASK, 785 WM8994_GPIO_DIR_OUTPUT); 786 787 /* DATA */ 788 ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK | 789 WM8994_GPIO_FUNCTION_MASK, 790 WM8994_GPIO_DIR_OUTPUT); 791 792 ret |= wm8994_init_volume_aif2_dac1(); 793 } 794 795 if (ret < 0) 796 goto err; 797 798 debug("%s: Codec chip init ok\n", __func__); 799 return 0; 800 err: 801 debug("%s: Codec chip init error\n", __func__); 802 return -1; 803 } 804 805 /* 806 * Gets fdt values for wm8994 config parameters 807 * 808 * @param pcodec_info codec information structure 809 * @param blob FDT blob 810 * @return int value, 0 for success 811 */ 812 static int get_codec_values(struct sound_codec_info *pcodec_info, 813 const void *blob) 814 { 815 int error = 0; 816 #if CONFIG_IS_ENABLED(OF_CONTROL) 817 enum fdt_compat_id compat; 818 int node; 819 int parent; 820 821 /* Get the node from FDT for codec */ 822 node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC); 823 if (node <= 0) { 824 debug("EXYNOS_SOUND: No node for codec in device tree\n"); 825 debug("node = %d\n", node); 826 return -1; 827 } 828 829 parent = fdt_parent_offset(blob, node); 830 if (parent < 0) { 831 debug("%s: Cannot find node parent\n", __func__); 832 return -1; 833 } 834 835 compat = fdtdec_lookup(blob, parent); 836 switch (compat) { 837 case COMPAT_SAMSUNG_S3C2440_I2C: 838 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent); 839 error |= pcodec_info->i2c_bus; 840 debug("i2c bus = %d\n", pcodec_info->i2c_bus); 841 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node, 842 "reg", 0); 843 error |= pcodec_info->i2c_dev_addr; 844 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr); 845 break; 846 default: 847 debug("%s: Unknown compat id %d\n", __func__, compat); 848 return -1; 849 } 850 #else 851 pcodec_info->i2c_bus = AUDIO_I2C_BUS; 852 pcodec_info->i2c_dev_addr = AUDIO_I2C_REG; 853 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr); 854 #endif 855 856 pcodec_info->codec_type = CODEC_WM_8994; 857 858 if (error == -1) { 859 debug("fail to get wm8994 codec node properties\n"); 860 return -1; 861 } 862 863 return 0; 864 } 865 866 /* WM8994 Device Initialisation */ 867 int wm8994_init(const void *blob, enum en_audio_interface aif_id, 868 int sampling_rate, int mclk_freq, 869 int bits_per_sample, unsigned int channels) 870 { 871 int ret = 0; 872 struct sound_codec_info *pcodec_info = &g_codec_info; 873 874 /* Get the codec Values */ 875 if (get_codec_values(pcodec_info, blob) < 0) { 876 debug("FDT Codec values failed\n"); 877 return -1; 878 } 879 880 /* shift the device address by 1 for 7 bit addressing */ 881 g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr; 882 wm8994_i2c_init(pcodec_info->i2c_bus); 883 884 if (pcodec_info->codec_type == CODEC_WM_8994) { 885 g_wm8994_info.type = WM8994; 886 } else { 887 debug("%s: Codec id [%d] not defined\n", __func__, 888 pcodec_info->codec_type); 889 return -1; 890 } 891 892 ret = wm8994_device_init(&g_wm8994_info, aif_id); 893 if (ret < 0) { 894 debug("%s: wm8994 codec chip init failed\n", __func__); 895 return ret; 896 } 897 898 ret = wm8994_set_sysclk(&g_wm8994_info, aif_id, WM8994_SYSCLK_MCLK1, 899 mclk_freq); 900 if (ret < 0) { 901 debug("%s: wm8994 codec set sys clock failed\n", __func__); 902 return ret; 903 } 904 905 ret = wm8994_hw_params(&g_wm8994_info, aif_id, sampling_rate, 906 bits_per_sample, channels); 907 908 if (ret == 0) { 909 ret = wm8994_set_fmt(aif_id, SND_SOC_DAIFMT_I2S | 910 SND_SOC_DAIFMT_NB_NF | 911 SND_SOC_DAIFMT_CBS_CFS); 912 } 913 return ret; 914 } 915
