1 #ifndef CAPSTONE_XCORE_H 2 #define CAPSTONE_XCORE_H 3 4 /* Capstone Disassembly Engine */ 5 /* By Nguyen Anh Quynh <aquynh (at) gmail.com>, 2014 */ 6 7 #ifdef __cplusplus 8 extern "C" { 9 #endif 10 11 #if !defined(_MSC_VER) || !defined(_KERNEL_MODE) 12 #include <stdint.h> 13 #endif 14 15 #include "platform.h" 16 17 #ifdef _MSC_VER 18 #pragma warning(disable:4201) 19 #endif 20 21 //> Operand type for instruction's operands 22 typedef enum xcore_op_type { 23 XCORE_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). 24 XCORE_OP_REG, // = CS_OP_REG (Register operand). 25 XCORE_OP_IMM, // = CS_OP_IMM (Immediate operand). 26 XCORE_OP_MEM, // = CS_OP_MEM (Memory operand). 27 } xcore_op_type; 28 29 // Instruction's operand referring to memory 30 // This is associated with XCORE_OP_MEM operand type above 31 typedef struct xcore_op_mem { 32 uint8_t base; // base register 33 uint8_t index; // index register 34 int32_t disp; // displacement/offset value 35 int direct; // +1: forward, -1: backward 36 } xcore_op_mem; 37 38 // Instruction operand 39 typedef struct cs_xcore_op { 40 xcore_op_type type; // operand type 41 union { 42 unsigned int reg; // register value for REG operand 43 int32_t imm; // immediate value for IMM operand 44 xcore_op_mem mem; // base/disp value for MEM operand 45 }; 46 } cs_xcore_op; 47 48 // Instruction structure 49 typedef struct cs_xcore { 50 // Number of operands of this instruction, 51 // or 0 when instruction has no operand. 52 uint8_t op_count; 53 cs_xcore_op operands[8]; // operands for this instruction. 54 } cs_xcore; 55 56 //> XCore registers 57 typedef enum xcore_reg { 58 XCORE_REG_INVALID = 0, 59 60 XCORE_REG_CP, 61 XCORE_REG_DP, 62 XCORE_REG_LR, 63 XCORE_REG_SP, 64 XCORE_REG_R0, 65 XCORE_REG_R1, 66 XCORE_REG_R2, 67 XCORE_REG_R3, 68 XCORE_REG_R4, 69 XCORE_REG_R5, 70 XCORE_REG_R6, 71 XCORE_REG_R7, 72 XCORE_REG_R8, 73 XCORE_REG_R9, 74 XCORE_REG_R10, 75 XCORE_REG_R11, 76 77 //> pseudo registers 78 XCORE_REG_PC, // pc 79 80 // internal thread registers 81 // see The-XMOS-XS1-Architecture(X7879A).pdf 82 XCORE_REG_SCP, // save pc 83 XCORE_REG_SSR, // save status 84 XCORE_REG_ET, // exception type 85 XCORE_REG_ED, // exception data 86 XCORE_REG_SED, // save exception data 87 XCORE_REG_KEP, // kernel entry pointer 88 XCORE_REG_KSP, // kernel stack pointer 89 XCORE_REG_ID, // thread ID 90 91 XCORE_REG_ENDING, // <-- mark the end of the list of registers 92 } xcore_reg; 93 94 //> XCore instruction 95 typedef enum xcore_insn { 96 XCORE_INS_INVALID = 0, 97 98 XCORE_INS_ADD, 99 XCORE_INS_ANDNOT, 100 XCORE_INS_AND, 101 XCORE_INS_ASHR, 102 XCORE_INS_BAU, 103 XCORE_INS_BITREV, 104 XCORE_INS_BLA, 105 XCORE_INS_BLAT, 106 XCORE_INS_BL, 107 XCORE_INS_BF, 108 XCORE_INS_BT, 109 XCORE_INS_BU, 110 XCORE_INS_BRU, 111 XCORE_INS_BYTEREV, 112 XCORE_INS_CHKCT, 113 XCORE_INS_CLRE, 114 XCORE_INS_CLRPT, 115 XCORE_INS_CLRSR, 116 XCORE_INS_CLZ, 117 XCORE_INS_CRC8, 118 XCORE_INS_CRC32, 119 XCORE_INS_DCALL, 120 XCORE_INS_DENTSP, 121 XCORE_INS_DGETREG, 122 XCORE_INS_DIVS, 123 XCORE_INS_DIVU, 124 XCORE_INS_DRESTSP, 125 XCORE_INS_DRET, 126 XCORE_INS_ECALLF, 127 XCORE_INS_ECALLT, 128 XCORE_INS_EDU, 129 XCORE_INS_EEF, 130 XCORE_INS_EET, 131 XCORE_INS_EEU, 132 XCORE_INS_ENDIN, 133 XCORE_INS_ENTSP, 134 XCORE_INS_EQ, 135 XCORE_INS_EXTDP, 136 XCORE_INS_EXTSP, 137 XCORE_INS_FREER, 138 XCORE_INS_FREET, 139 XCORE_INS_GETD, 140 XCORE_INS_GET, 141 XCORE_INS_GETN, 142 XCORE_INS_GETR, 143 XCORE_INS_GETSR, 144 XCORE_INS_GETST, 145 XCORE_INS_GETTS, 146 XCORE_INS_INCT, 147 XCORE_INS_INIT, 148 XCORE_INS_INPW, 149 XCORE_INS_INSHR, 150 XCORE_INS_INT, 151 XCORE_INS_IN, 152 XCORE_INS_KCALL, 153 XCORE_INS_KENTSP, 154 XCORE_INS_KRESTSP, 155 XCORE_INS_KRET, 156 XCORE_INS_LADD, 157 XCORE_INS_LD16S, 158 XCORE_INS_LD8U, 159 XCORE_INS_LDA16, 160 XCORE_INS_LDAP, 161 XCORE_INS_LDAW, 162 XCORE_INS_LDC, 163 XCORE_INS_LDW, 164 XCORE_INS_LDIVU, 165 XCORE_INS_LMUL, 166 XCORE_INS_LSS, 167 XCORE_INS_LSUB, 168 XCORE_INS_LSU, 169 XCORE_INS_MACCS, 170 XCORE_INS_MACCU, 171 XCORE_INS_MJOIN, 172 XCORE_INS_MKMSK, 173 XCORE_INS_MSYNC, 174 XCORE_INS_MUL, 175 XCORE_INS_NEG, 176 XCORE_INS_NOT, 177 XCORE_INS_OR, 178 XCORE_INS_OUTCT, 179 XCORE_INS_OUTPW, 180 XCORE_INS_OUTSHR, 181 XCORE_INS_OUTT, 182 XCORE_INS_OUT, 183 XCORE_INS_PEEK, 184 XCORE_INS_REMS, 185 XCORE_INS_REMU, 186 XCORE_INS_RETSP, 187 XCORE_INS_SETCLK, 188 XCORE_INS_SET, 189 XCORE_INS_SETC, 190 XCORE_INS_SETD, 191 XCORE_INS_SETEV, 192 XCORE_INS_SETN, 193 XCORE_INS_SETPSC, 194 XCORE_INS_SETPT, 195 XCORE_INS_SETRDY, 196 XCORE_INS_SETSR, 197 XCORE_INS_SETTW, 198 XCORE_INS_SETV, 199 XCORE_INS_SEXT, 200 XCORE_INS_SHL, 201 XCORE_INS_SHR, 202 XCORE_INS_SSYNC, 203 XCORE_INS_ST16, 204 XCORE_INS_ST8, 205 XCORE_INS_STW, 206 XCORE_INS_SUB, 207 XCORE_INS_SYNCR, 208 XCORE_INS_TESTCT, 209 XCORE_INS_TESTLCL, 210 XCORE_INS_TESTWCT, 211 XCORE_INS_TSETMR, 212 XCORE_INS_START, 213 XCORE_INS_WAITEF, 214 XCORE_INS_WAITET, 215 XCORE_INS_WAITEU, 216 XCORE_INS_XOR, 217 XCORE_INS_ZEXT, 218 219 XCORE_INS_ENDING, // <-- mark the end of the list of instructions 220 } xcore_insn; 221 222 //> Group of XCore instructions 223 typedef enum xcore_insn_group { 224 XCORE_GRP_INVALID = 0, // = CS_GRP_INVALID 225 226 //> Generic groups 227 // all jump instructions (conditional+direct+indirect jumps) 228 XCORE_GRP_JUMP, // = CS_GRP_JUMP 229 230 XCORE_GRP_ENDING, // <-- mark the end of the list of groups 231 } xcore_insn_group; 232 233 #ifdef __cplusplus 234 } 235 #endif 236 237 #endif 238
