1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012-2013, Xilinx, Michal Simek 4 * 5 * (C) Copyright 2002 6 * Rich Ireland, Enterasys Networks, rireland (at) enterasys.com. 7 * Keith Outwater, keith_outwater (at) mvis.com 8 */ 9 10 /* 11 * Xilinx FPGA support 12 */ 13 14 #include <common.h> 15 #include <fpga.h> 16 #include <virtex2.h> 17 #include <spartan2.h> 18 #include <spartan3.h> 19 #include <zynqpl.h> 20 21 /* Local Static Functions */ 22 static int xilinx_validate(xilinx_desc *desc, char *fn); 23 24 /* ------------------------------------------------------------------------- */ 25 26 int fpga_is_partial_data(int devnum, size_t img_len) 27 { 28 const fpga_desc * const desc = fpga_get_desc(devnum); 29 xilinx_desc *desc_xilinx = desc->devdesc; 30 31 /* Check datasize against FPGA size */ 32 if (img_len >= desc_xilinx->size) 33 return 0; 34 35 /* datasize is smaller, must be partial data */ 36 return 1; 37 } 38 39 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, 40 bitstream_type bstype) 41 { 42 unsigned int length; 43 unsigned int swapsize; 44 unsigned char *dataptr; 45 unsigned int i; 46 const fpga_desc *desc; 47 xilinx_desc *xdesc; 48 49 dataptr = (unsigned char *)fpgadata; 50 /* Find out fpga_description */ 51 desc = fpga_validate(devnum, dataptr, 0, (char *)__func__); 52 /* Assign xilinx device description */ 53 xdesc = desc->devdesc; 54 55 /* skip the first bytes of the bitsteam, their meaning is unknown */ 56 length = (*dataptr << 8) + *(dataptr + 1); 57 dataptr += 2; 58 dataptr += length; 59 60 /* get design name (identifier, length, string) */ 61 length = (*dataptr << 8) + *(dataptr + 1); 62 dataptr += 2; 63 if (*dataptr++ != 0x61) { 64 debug("%s: Design name id not recognized in bitstream\n", 65 __func__); 66 return FPGA_FAIL; 67 } 68 69 length = (*dataptr << 8) + *(dataptr + 1); 70 dataptr += 2; 71 printf(" design filename = \"%s\"\n", dataptr); 72 dataptr += length; 73 74 /* get part number (identifier, length, string) */ 75 if (*dataptr++ != 0x62) { 76 printf("%s: Part number id not recognized in bitstream\n", 77 __func__); 78 return FPGA_FAIL; 79 } 80 81 length = (*dataptr << 8) + *(dataptr + 1); 82 dataptr += 2; 83 84 if (xdesc->name) { 85 i = (ulong)strstr((char *)dataptr, xdesc->name); 86 if (!i) { 87 printf("%s: Wrong bitstream ID for this device\n", 88 __func__); 89 printf("%s: Bitstream ID %s, current device ID %d/%s\n", 90 __func__, dataptr, devnum, xdesc->name); 91 return FPGA_FAIL; 92 } 93 } else { 94 printf("%s: Please fill correct device ID to xilinx_desc\n", 95 __func__); 96 } 97 printf(" part number = \"%s\"\n", dataptr); 98 dataptr += length; 99 100 /* get date (identifier, length, string) */ 101 if (*dataptr++ != 0x63) { 102 printf("%s: Date identifier not recognized in bitstream\n", 103 __func__); 104 return FPGA_FAIL; 105 } 106 107 length = (*dataptr << 8) + *(dataptr+1); 108 dataptr += 2; 109 printf(" date = \"%s\"\n", dataptr); 110 dataptr += length; 111 112 /* get time (identifier, length, string) */ 113 if (*dataptr++ != 0x64) { 114 printf("%s: Time identifier not recognized in bitstream\n", 115 __func__); 116 return FPGA_FAIL; 117 } 118 119 length = (*dataptr << 8) + *(dataptr+1); 120 dataptr += 2; 121 printf(" time = \"%s\"\n", dataptr); 122 dataptr += length; 123 124 /* get fpga data length (identifier, length) */ 125 if (*dataptr++ != 0x65) { 126 printf("%s: Data length id not recognized in bitstream\n", 127 __func__); 128 return FPGA_FAIL; 129 } 130 swapsize = ((unsigned int) *dataptr << 24) + 131 ((unsigned int) *(dataptr + 1) << 16) + 132 ((unsigned int) *(dataptr + 2) << 8) + 133 ((unsigned int) *(dataptr + 3)); 134 dataptr += 4; 135 printf(" bytes in bitstream = %d\n", swapsize); 136 137 return fpga_load(devnum, dataptr, swapsize, bstype); 138 } 139 140 int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, 141 bitstream_type bstype) 142 { 143 if (!xilinx_validate (desc, (char *)__FUNCTION__)) { 144 printf ("%s: Invalid device descriptor\n", __FUNCTION__); 145 return FPGA_FAIL; 146 } 147 148 if (!desc->operations || !desc->operations->load) { 149 printf("%s: Missing load operation\n", __func__); 150 return FPGA_FAIL; 151 } 152 153 return desc->operations->load(desc, buf, bsize, bstype); 154 } 155 156 #if defined(CONFIG_CMD_FPGA_LOADFS) 157 int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, 158 fpga_fs_info *fpga_fsinfo) 159 { 160 if (!xilinx_validate(desc, (char *)__func__)) { 161 printf("%s: Invalid device descriptor\n", __func__); 162 return FPGA_FAIL; 163 } 164 165 if (!desc->operations || !desc->operations->loadfs) { 166 printf("%s: Missing loadfs operation\n", __func__); 167 return FPGA_FAIL; 168 } 169 170 return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo); 171 } 172 #endif 173 174 #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) 175 int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize, 176 struct fpga_secure_info *fpga_sec_info) 177 { 178 if (!xilinx_validate(desc, (char *)__func__)) { 179 printf("%s: Invalid device descriptor\n", __func__); 180 return FPGA_FAIL; 181 } 182 183 if (!desc->operations || !desc->operations->loads) { 184 printf("%s: Missing loads operation\n", __func__); 185 return FPGA_FAIL; 186 } 187 188 return desc->operations->loads(desc, buf, bsize, fpga_sec_info); 189 } 190 #endif 191 192 int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) 193 { 194 if (!xilinx_validate (desc, (char *)__FUNCTION__)) { 195 printf ("%s: Invalid device descriptor\n", __FUNCTION__); 196 return FPGA_FAIL; 197 } 198 199 if (!desc->operations || !desc->operations->dump) { 200 printf("%s: Missing dump operation\n", __func__); 201 return FPGA_FAIL; 202 } 203 204 return desc->operations->dump(desc, buf, bsize); 205 } 206 207 int xilinx_info(xilinx_desc *desc) 208 { 209 int ret_val = FPGA_FAIL; 210 211 if (xilinx_validate (desc, (char *)__FUNCTION__)) { 212 printf ("Family: \t"); 213 switch (desc->family) { 214 case xilinx_spartan2: 215 printf ("Spartan-II\n"); 216 break; 217 case xilinx_spartan3: 218 printf ("Spartan-III\n"); 219 break; 220 case xilinx_virtex2: 221 printf ("Virtex-II\n"); 222 break; 223 case xilinx_zynq: 224 printf("Zynq PL\n"); 225 break; 226 case xilinx_zynqmp: 227 printf("ZynqMP PL\n"); 228 break; 229 /* Add new family types here */ 230 default: 231 printf ("Unknown family type, %d\n", desc->family); 232 } 233 234 printf ("Interface type:\t"); 235 switch (desc->iface) { 236 case slave_serial: 237 printf ("Slave Serial\n"); 238 break; 239 case master_serial: /* Not used */ 240 printf ("Master Serial\n"); 241 break; 242 case slave_parallel: 243 printf ("Slave Parallel\n"); 244 break; 245 case jtag_mode: /* Not used */ 246 printf ("JTAG Mode\n"); 247 break; 248 case slave_selectmap: 249 printf ("Slave SelectMap Mode\n"); 250 break; 251 case master_selectmap: 252 printf ("Master SelectMap Mode\n"); 253 break; 254 case devcfg: 255 printf("Device configuration interface (Zynq)\n"); 256 break; 257 case csu_dma: 258 printf("csu_dma configuration interface (ZynqMP)\n"); 259 break; 260 /* Add new interface types here */ 261 default: 262 printf ("Unsupported interface type, %d\n", desc->iface); 263 } 264 265 printf("Device Size: \t%zd bytes\n" 266 "Cookie: \t0x%x (%d)\n", 267 desc->size, desc->cookie, desc->cookie); 268 if (desc->name) 269 printf("Device name: \t%s\n", desc->name); 270 271 if (desc->iface_fns) 272 printf ("Device Function Table @ 0x%p\n", desc->iface_fns); 273 else 274 printf ("No Device Function Table.\n"); 275 276 if (desc->operations && desc->operations->info) 277 desc->operations->info(desc); 278 279 ret_val = FPGA_SUCCESS; 280 } else { 281 printf ("%s: Invalid device descriptor\n", __FUNCTION__); 282 } 283 284 return ret_val; 285 } 286 287 /* ------------------------------------------------------------------------- */ 288 289 static int xilinx_validate(xilinx_desc *desc, char *fn) 290 { 291 int ret_val = false; 292 293 if (desc) { 294 if ((desc->family > min_xilinx_type) && 295 (desc->family < max_xilinx_type)) { 296 if ((desc->iface > min_xilinx_iface_type) && 297 (desc->iface < max_xilinx_iface_type)) { 298 if (desc->size) { 299 ret_val = true; 300 } else 301 printf ("%s: NULL part size\n", fn); 302 } else 303 printf ("%s: Invalid Interface type, %d\n", 304 fn, desc->iface); 305 } else 306 printf ("%s: Invalid family type, %d\n", fn, desc->family); 307 } else 308 printf ("%s: NULL descriptor!\n", fn); 309 310 return ret_val; 311 } 312
