| /external/tensorflow/tensorflow/java/src/main/java/org/tensorflow/op/ |
| Op.java | 16 package org.tensorflow.op;
27 * // All values returned by an Ops call can be referred as a Op
28 * Op split = ops.array().split(...);
29 * Op shape = ops.array().shape(...);
31 * // All operations could be added to an Op collection
32 * Collection<Op> allOps = Arrays.asList(split, shape);
35 public interface Op {}
|
| /cts/tests/tests/graphics/src/android/graphics/cts/ |
| Region_OpTest.java | 21 import android.graphics.Region.Op;
34 assertEquals(Op.DIFFERENCE, Op.valueOf("DIFFERENCE"));
35 assertEquals(Op.INTERSECT, Op.valueOf("INTERSECT"));
36 assertEquals(Op.UNION, Op.valueOf("UNION"));
37 assertEquals(Op.XOR, Op.valueOf("XOR"));
38 assertEquals(Op.REVERSE_DIFFERENCE, Op.valueOf("REVERSE_DIFFERENCE"))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 59 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
61 switch (MI->getOperand(Op).getImm()) {
80 const MCOperand &Op = MI->getOperand(OpNo);
81 if (Op.isImm())
83 O << (int)Op.getImm();
85 assert(Op.isExpr() && "unknown pcrel immediate operand");
86 O << *Op.getExpr();
92 const MCOperand &Op = MI->getOperand(OpNo);
93 if (Op.isReg()) {
94 O << '%' << getRegisterName(Op.getReg())
[all...] |
| X86IntelInstPrinter.cpp | 49 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
51 switch (MI->getOperand(Op).getImm()) {
68 const MCOperand &Op = MI->getOperand(OpNo);
69 if (Op.isImm())
70 O << Op.getImm();
72 assert(Op.isExpr() && "unknown pcrel immediate operand");
73 O << *Op.getExpr();
84 const MCOperand &Op = MI->getOperand(OpNo);
85 if (Op.isReg()) {
86 PrintRegName(O, getRegisterName(Op.getReg()))
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/DebugInfo/DWARF/ |
| DWARFExpression.cpp | 27 typedef DWARFExpression::Operation Op;
28 typedef Op::Description Desc;
31 Descriptions[DW_OP_addr] = Desc(Op::Dwarf2, Op::SizeAddr);
32 Descriptions[DW_OP_deref] = Desc(Op::Dwarf2);
33 Descriptions[DW_OP_const1u] = Desc(Op::Dwarf2, Op::Size1);
34 Descriptions[DW_OP_const1s] = Desc(Op::Dwarf2, Op::SignedSize1);
35 Descriptions[DW_OP_const2u] = Desc(Op::Dwarf2, Op::Size2)
[all...] |
| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| SPIRVOpCode.h | 51 SPIRVMap<Op, std::string>::init() {
52 #define _SPIRV_OP(x, ...) add(Op##x, #x);
56 SPIRV_DEF_NAMEMAP(Op, OpCodeNameMap)
58 inline bool isAtomicOpCode(Op OpCode) {
65 inline bool isBinaryOpCode(Op OpCode) {
71 inline bool isShiftOpCode(Op OpCode) {
76 inline bool isLogicalOpCode(Op OpCode) {
81 inline bool isBitwiseOpCode(Op OpCode) {
86 inline bool isBinaryShiftLogicalBitwiseOpCode(Op OpCode) {
92 inline bool isCmpOpCode(Op OpCode)
[all...] |
| /external/v8/tools/clang/rewrite_to_chrome_style/tests/ |
| operators-expected.cc | 7 struct Op {
8 bool operator==(const Op&) { return true; }
20 blink::Op a, b;
|
| operators-original.cc | 7 struct Op {
8 bool operator==(const Op&) { return true; }
20 blink::Op a, b;
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 589 MachineOperand Op(MachineOperand::MO_Immediate);
590 Op.setImm(Val);
591 return Op;
595 MachineOperand Op(MachineOperand::MO_CImmediate);
596 Op.Contents.CI = CI;
597 return Op;
601 MachineOperand Op(MachineOperand::MO_FPImmediate);
602 Op.Contents.CFP = CFP;
603 return Op;
615 MachineOperand Op(MachineOperand::MO_Register)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/InstPrinter/ |
| BPFInstPrinter.cpp | 54 const MCOperand &Op = MI->getOperand(OpNo);
55 if (Op.isReg()) {
56 O << getRegisterName(Op.getReg());
57 } else if (Op.isImm()) {
58 O << formatImm((int32_t)Op.getImm());
60 assert(Op.isExpr() && "Expected an expression");
61 printExpr(Op.getExpr(), O);
88 const MCOperand &Op = MI->getOperand(OpNo);
89 if (Op.isImm())
90 O << formatImm(Op.getImm())
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 80 const MCOperand &Op = MI->getOperand(OpNo);
81 if (Op.isReg()) {
82 printRegName(O, Op.getReg());
83 } else if (Op.isImm()) {
85 int64_t Imm = Op.getImm();
104 assert(Op.isExpr() && "unknown operand kind in printOperand");
106 Op.getExpr()->print(O, &MAI);
111 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
113 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
114 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg)
[all...] |
| X86IntelInstPrinter.cpp | 60 const MCOperand &Op = MI->getOperand(OpNo);
61 if (Op.isReg()) {
62 printRegName(O, Op.getReg());
63 } else if (Op.isImm()) {
64 O << formatImm((int64_t)Op.getImm());
66 assert(Op.isExpr() && "unknown operand kind in printOperand");
68 Op.getExpr()->print(O, &MAI);
72 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
74 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
75 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm()
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 112 MCOperand Op;
113 Op.Kind = kRegister;
114 Op.RegVal = Reg;
115 return Op;
118 MCOperand Op;
119 Op.Kind = kImmediate;
120 Op.ImmVal = Val;
121 return Op;
124 MCOperand Op;
125 Op.Kind = kFPImmediate
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| MCInst.h | 117 MCOperand Op;
118 Op.Kind = kRegister;
119 Op.RegVal = Reg;
120 return Op;
124 MCOperand Op;
125 Op.Kind = kImmediate;
126 Op.ImmVal = Val;
127 return Op;
131 MCOperand Op;
132 Op.Kind = kFPImmediate
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 54 SDValue LegalizeOp(SDValue Op);
56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
58 SDValue UnrollVSETCC(SDValue Op);
63 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
66 SDValue ExpandVSELECT(SDValue Op);
67 SDValue ExpandFNEG(SDValue Op);
71 SDValue PromoteVectorOp(SDValue Op);
104 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
106 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
107 AddLegalizedOperand(Op.getValue(i), Result.getValue(i))
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 54 SDValue LegalizeOp(SDValue Op);
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
60 SDValue UnrollVSETCC(SDValue Op);
66 SDValue Expand(SDValue Op);
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
76 SDValue ExpandSEXTINREG(SDValue Op);
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
99 SDValue ExpandBSWAP(SDValue Op);
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 72 void X86ATTInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op,
74 int64_t Imm = MI->getOperand(Op).getImm();
112 void X86ATTInstPrinter::printXOPCC(const MCInst *MI, unsigned Op,
114 int64_t Imm = MI->getOperand(Op).getImm();
128 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
144 const MCOperand &Op = MI->getOperand(OpNo);
145 if (Op.isImm())
146 O << formatImm(Op.getImm());
148 assert(Op.isExpr() && "unknown pcrel immediate operand")
[all...] |
| X86IntelInstPrinter.cpp | 54 void X86IntelInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op,
56 int64_t Imm = MI->getOperand(Op).getImm();
94 void X86IntelInstPrinter::printXOPCC(const MCInst *MI, unsigned Op,
96 int64_t Imm = MI->getOperand(Op).getImm();
110 void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
112 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
125 const MCOperand &Op = MI->getOperand(OpNo);
126 if (Op.isImm())
127 O << formatImm(Op.getImm());
129 assert(Op.isExpr() && "unknown pcrel immediate operand")
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| MCWin64EH.h | 36 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg)
37 : Operation(Op), Label(L), Offset(0), Register(Reg) {
38 assert(Op == Win64EH::UOP_PushNonVol);
43 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg, unsigned Off)
44 : Operation(Op), Label(L), Offset(Off), Register(Reg) {
45 assert(Op == Win64EH::UOP_SetFPReg ||
46 Op == Win64EH::UOP_SaveNonVol ||
47 Op == Win64EH::UOP_SaveNonVolBig ||
48 Op == Win64EH::UOP_SaveXMM128 ||
49 Op == Win64EH::UOP_SaveXMM128Big)
[all...] |
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 37 const MCOperand &Op = MI->getOperand(OpNo);
38 if (Op.isImm())
39 O << Op.getImm();
41 assert(Op.isExpr() && "unknown pcrel immediate operand");
42 Op.getExpr()->print(O, &MAI);
49 const MCOperand &Op = MI->getOperand(OpNo);
50 if (Op.isReg()) {
51 O << getRegisterName(Op.getReg());
52 } else if (Op.isImm()) {
53 O << '#' << Op.getImm()
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 36 const MCOperand &Op = MI->getOperand(OpNo);
37 if (Op.isImm())
38 O << Op.getImm();
40 assert(Op.isExpr() && "unknown pcrel immediate operand");
41 O << *Op.getExpr();
48 const MCOperand &Op = MI->getOperand(OpNo);
49 if (Op.isReg()) {
50 O << getRegisterName(Op.getReg());
51 } else if (Op.isImm()) {
52 O << '#' << Op.getImm()
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 37 const MCOperand &Op = MI->getOperand(OpNo);
38 if (Op.isImm())
39 O << Op.getImm();
41 assert(Op.isExpr() && "unknown pcrel immediate operand");
42 Op.getExpr()->print(O, &MAI);
49 const MCOperand &Op = MI->getOperand(OpNo);
50 if (Op.isReg()) {
51 O << getRegisterName(Op.getReg());
52 } else if (Op.isImm()) {
53 O << '#' << Op.getImm()
[all...] |
| /external/llvm/tools/llvm-cov/ |
| CoverageFilters.h | 60 Operation Op;
63 StatisticThresholdFilter(Operation Op, T Threshold)
64 : Op(Op), Threshold(Threshold) {}
69 switch (Op) {
84 RegionCoverageFilter(Operation Op, double Threshold)
85 : StatisticThresholdFilter(Op, Threshold) {}
95 LineCoverageFilter(Operation Op, double Threshold)
96 : StatisticThresholdFilter(Op, Threshold) {}
|
| /external/skia/src/gpu/ |
| GrDrawOpTest.h | 28 #define GR_DRAW_OP_TEST_DEFINE(Op) \
29 std::unique_ptr<GrDrawOp> Op##__Test(GrPaint&& paint, SkRandom* random, \
31 #define GR_DRAW_OP_TEST_FRIEND(Op) \
32 friend std::unique_ptr<GrDrawOp> Op##__Test(GrPaint&& paint, SkRandom* random, \
35 /** Helper for op test factories to pick a random stencil state. */
|
| /external/skqp/src/gpu/ |
| GrDrawOpTest.h | 26 #define GR_DRAW_OP_TEST_DEFINE(Op) \
27 std::unique_ptr<GrDrawOp> Op##__Test(GrPaint&& paint, SkRandom* random, GrContext* context, \
29 #define GR_DRAW_OP_TEST_FRIEND(Op) \
30 friend std::unique_ptr<GrDrawOp> Op##__Test(GrPaint&& paint, SkRandom* random, \
33 /** Helper for op test factories to pick a random stencil state. */
|
