| /external/vixl/test/aarch32/ |
| test-disasm-a32.cc | 510 "adc r0, #1\n");
573 "adc r0, r2, lsl #1\n");
581 "adc r0, r1, asr #3\n");
594 "adc r0, ip, r0\n");
604 "adc r0, ip\n");
614 "adc r0, ip\n");
623 COMPARE_T32(Adc(r0, r1, Operand(r2, LSL, r3)),
625 "adc r0, r1, r0\n");
[all...] |
| test-assembler-aarch32.cc | 227 // TODO: Add SBC to the ADC tests.
243 __ Adc(r4, r2, r3);
244 __ Adc(r5, r0, Operand(r1, LSL, 30));
245 __ Adc(r6, r0, Operand(r2, LSR, 16));
246 __ Adc(r7, r2, Operand(r3, ASR, 4));
247 __ Adc(r8, r2, Operand(r3, ROR, 8));
248 __ Adc(r9, r2, Operand(r3, RRX));
271 __ Adc(r5, r2, r3);
272 __ Adc(r6, r0, Operand(r1, LSL, 30));
273 __ Adc(r7, r0, Operand(r2, LSR, 16))
[all...] |
| test-simulator-cond-rd-rn-operand-rm-a32.cc | 116 M(Adc) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-t32.cc | 116 M(Adc) \
[all...] |
| test-simulator-cond-rd-rn-operand-const-a32.cc | 116 M(Adc) \
[all...] |
| test-simulator-cond-rd-rn-operand-const-t32.cc | 116 M(Adc) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 116 M(Adc) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 116 M(Adc) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 116 M(Adc) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 116 M(Adc) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 116 M(Adc) \
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm_vixl.h | 82 WITH_FLAGS_DONT_CARE_RD_RN_OP(Adc);
|
| /external/swiftshader/third_party/subzero/src/ |
| IceInstARM32.h | 381 Adc,
[all...] |
| IceInstX86Base.h | 76 Adc,
[all...] |
| IceTargetLoweringX86Base.h | 518 Context.insert<typename Traits::Insts::Adc>(Dest, Src0);
[all...] |
| IceInstARM32.cpp | 552 Asm->adc(getDest(), getSrc(0), getSrc(1), SetFlags, getPredicate());
[all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | [all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 182 void TurboAssembler::Adc(const Register& rd, const Register& rn,
186 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, ADC);
195 AddSubWithCarryMacro(rd, rn, operand, SetFlags, ADC);
[all...] |
| macro-assembler-arm64.h | [all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | [all...] |
| /art/compiler/optimizing/ |
| code_generator_arm_vixl.cc | [all...] |
| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | [all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.cc | [all...] |
| macro-assembler-aarch64.h | 688 void Adc(const Register& rd, const Register& rn, const Operand& operand);
[all...] |
