| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 66 unsigned MulOpc, unsigned AddSubOpc,
207 unsigned MulOpc, unsigned AddSubOpc,
222 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
292 unsigned MulOpc, AddSubOpc;
295 MulOpc, AddSubOpc, NegAcc, HasLane) ||
299 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane);
|
| ARMBaseInstrInfo.h | 282 unsigned &AddSubOpc, bool &NegAcc,
|
| ARMBaseInstrInfo.cpp | 57 unsigned AddSubOpc; // Expanded add / sub opcode
63 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 69 unsigned MulOpc, unsigned AddSubOpc,
273 unsigned MulOpc, unsigned AddSubOpc,
288 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
360 unsigned MulOpc, AddSubOpc;
363 MulOpc, AddSubOpc, NegAcc, HasLane) ||
367 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane);
|
| ARMBaseInstrInfo.h | 383 unsigned &AddSubOpc, bool &NegAcc,
|
| ARMBaseInstrInfo.cpp | 58 uint16_t AddSubOpc; // Expanded add / sub opcode
64 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
92 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 69 unsigned MulOpc, unsigned AddSubOpc,
273 unsigned MulOpc, unsigned AddSubOpc,
288 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
357 unsigned MulOpc, AddSubOpc;
360 MulOpc, AddSubOpc, NegAcc, HasLane) ||
364 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane);
|
| ARMBaseInstrInfo.h | 414 unsigned &AddSubOpc, bool &NegAcc,
|
| ARMBaseInstrInfo.cpp | 82 uint16_t AddSubOpc; // Expanded add / sub opcode
88 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
116 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
