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    Searched refs:AddrIdx (Results 1 - 9 of 9) sorted by null

  /external/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCNaCl.h 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
MipsNaClELFStreamer.cpp 116 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx,
122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
149 unsigned AddrIdx;
151 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx,
156 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx)
162 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter);
202 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
223 *AddrIdx = 1;
234 *AddrIdx = 1;
242 *AddrIdx = 2
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCNaCl.h 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
MipsNaClELFStreamer.cpp 125 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx,
131 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
158 unsigned AddrIdx;
160 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx,
165 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx)
171 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter);
211 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
232 *AddrIdx = 1;
243 *AddrIdx = 1;
251 *AddrIdx = 2
    [all...]
  /external/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 171 int AddrIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::addr);
172 const MachineOperand &AddrReg0 = I->getOperand(AddrIdx);
173 const MachineOperand &AddrReg1 = MBBI->getOperand(AddrIdx);
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 314 int AddrIdx[3];
339 AddrIdx[i] = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AddrOpName[i]);
340 AddrReg[i] = &CI.I->getOperand(AddrIdx[i]);
405 const MachineOperand &AddrRegNext = MBBI->getOperand(AddrIdx[i]);
    [all...]
SIISelLowering.cpp     [all...]
  /external/llvm/lib/Target/Mips/
MipsDelaySlotFiller.cpp 685 unsigned AddrIdx;
686 if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
687 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
MipsDelaySlotFiller.cpp 712 unsigned AddrIdx;
713 if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
714 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||

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