/external/u-boot/drivers/net/phy/ |
natsemi.c | 21 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 57 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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et1011c.c | 36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET);
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realtek.c | 82 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 128 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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marvell.c | 135 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 143 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 512 reg |= BMCR_RESET; 613 reg |= BMCR_RESET;
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phy.c | 798 if (phy_write(phydev, devad, MII_BMCR, BMCR_RESET) < 0) { 812 while ((reg & BMCR_RESET) && timeout--) { 822 if (reg & BMCR_RESET) {
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mscc.c | 254 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, (reg_val | BMCR_RESET)); 258 while ((reg_val & BMCR_RESET) && (timeout > 0)) {
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broadcom.c | 138 reg |= BMCR_RESET;
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/external/u-boot/board/egnite/ethernut5/ |
ethernut5.c | 174 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
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/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Phy/MvPhyDxe/ |
MvPhyDxe.h | 70 #define BMCR_RESET 0x8000 /* Reset the DP83840 */
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MvPhyDxe.c | 74 Reg |= BMCR_RESET;
77 while ((Reg & BMCR_RESET) && timeout--) {
82 if (Reg & BMCR_RESET) {
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/bionic/libc/kernel/uapi/linux/ |
mii.h | 56 #define BMCR_RESET 0x8000
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mdio.h | 73 #define MDIO_CTRL1_RESET BMCR_RESET
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/external/kernel-headers/original/uapi/linux/ |
mii.h | 51 #define BMCR_RESET 0x8000 /* Reset to default state */
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mdio.h | 80 #define MDIO_CTRL1_RESET BMCR_RESET
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/external/u-boot/drivers/qe/ |
uec_phy.c | 263 ctrl |= BMCR_RESET; 334 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); 511 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); 584 BMCR_RESET);
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/external/u-boot/include/linux/ |
mii.h | 46 #define BMCR_RESET 0x8000 /* Reset the DP83840 */
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mdio.h | 75 #define MDIO_CTRL1_RESET BMCR_RESET
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/external/u-boot/drivers/net/ |
smc911x.c | 87 smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET);
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ax88180.c | 116 ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE)); 119 while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
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ag7xxx.c | 720 BMCR_ANENABLE | BMCR_RESET); 733 } while (ret & BMCR_RESET);
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fec_mxc.c | 207 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); [all...] |
/device/linaro/bootloader/edk2/OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772/ |
Ax88772.h | 231 #define BMCR_RESET 0x8000 ///< 1 = Reset the PHY, bit clears after reset
[all...] |
Ax88772.c | 632 BMCR_RESET );
[all...] |
/external/u-boot/common/ |
miiphyutil.c | 358 if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) {
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/device/linaro/bootloader/edk2/OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/ |
Ax88772.h | 257 #define BMCR_RESET 0x8000 ///< 1 = Reset the PHY, bit clears after reset
[all...] |