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Searched
refs:CCM_PLL5_CTRL_DDR_CLK
(Results
1 - 2
of
2
) sorted by null
/external/u-boot/arch/arm/include/asm/arch-sunxi/
clock_sun4i.h
241
#define
CCM_PLL5_CTRL_DDR_CLK
(0x1 << 29)
/external/u-boot/arch/arm/mach-sunxi/
dram_sun4i.c
291
setbits_le32(&ccm->pll5_cfg,
CCM_PLL5_CTRL_DDR_CLK
);
Completed in 54 milliseconds