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Searched refs:CLK_DIV_CORE0_VAL (Results 1 -
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| /external/u-boot/arch/arm/mach-exynos/ | |
| exynos5_setup.h | 133 #define CLK_DIV_CORE0_VAL 0x00120000 |
| clock_init_exynos5.c | 670 writel(CLK_DIV_CORE0_VAL, &clk->div_core0); |
Completed in 49 milliseconds
