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    Searched refs:CLK_DIV_CPERI1_VAL (Results 1 - 2 of 2) sorted by null

  /external/u-boot/arch/arm/mach-exynos/
exynos5_setup.h 699 #define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
884 #define CLK_DIV_CPERI1_VAL 0x3f3f0000
clock_init_exynos5.c 958 writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);

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