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    Searched refs:CLK_DIV_ISP0_VAL (Results 1 - 2 of 2) sorted by null

  /external/u-boot/arch/arm/mach-exynos/
exynos5_setup.h 483 #define CLK_DIV_ISP0_VAL 0x31
750 #define CLK_DIV_ISP0_VAL 0x13131300
clock_init_exynos5.c 768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);

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